[llvm] a6a6d11 - [MC][ARM] Fix number of operands of tMOVSr

[Evgeny Leviant via llvm-commits]

Author: Evgeny Leviant
Date: 2020-11-24T18:13:10+03:00
New Revision: a6a6d11c7b05b5b317818246e09ededda671f0b9

URL: https://github.com/llvm/llvm-project/commit/a6a6d11c7b05b5b317818246e09ededda671f0b9
DIFF: https://github.com/llvm/llvm-project/commit/a6a6d11c7b05b5b317818246e09ededda671f0b9.diff

LOG: [MC][ARM] Fix number of operands of tMOVSr

Differential revision: https://reviews.llvm.org/D92029

Added: 
    llvm/test/MC/ARM/tMOVSr.s

Modified: 
    llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 090ee8c44333..05f049983764 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -10309,11 +10309,14 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
         !HasWideQualifier) {
       // The operands aren't the same for tMOV[S]r... (no cc_out)
       MCInst TmpInst;
-      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
+      unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr;
+      TmpInst.setOpcode(Op);
       TmpInst.addOperand(Inst.getOperand(0));
       TmpInst.addOperand(Inst.getOperand(1));
-      TmpInst.addOperand(Inst.getOperand(2));
-      TmpInst.addOperand(Inst.getOperand(3));
+      if (Op == ARM::tMOVr) {
+        TmpInst.addOperand(Inst.getOperand(2));
+        TmpInst.addOperand(Inst.getOperand(3));
+      }
       Inst = TmpInst;
       return true;
     }

diff  --git a/llvm/test/MC/ARM/tMOVSr.s b/llvm/test/MC/ARM/tMOVSr.s
new file mode 100644
index 000000000000..198c90aa5ceb
--- /dev/null
+++ b/llvm/test/MC/ARM/tMOVSr.s
@@ -0,0 +1,6 @@
+@ REQUIRES: asserts
+@ RUN: llvm-mc --triple=thumbv8 --debug %s 2>&1 | FileCheck %s --match-full-lines
+
+@ CHECK: Changed to: <MCInst #{{[0-9]+}} tMOVSr <MCOperand Reg:{{[0-9]+}}> <MCOperand Reg:{{[0-9]+}}>>
+.text
+  movs r2, r3