[llvm] 78caf4f - [SchedModels] Limit set of predicates seen by mutuallyExclusive

[Evgeny Leviant via llvm-commits]

Author: Evgeny Leviant
Date: 2020-11-24T12:44:10+03:00
New Revision: 78caf4f1bb13c4cf2af3ee9d9f8ff16f67a177c7

URL: https://github.com/llvm/llvm-project/commit/78caf4f1bb13c4cf2af3ee9d9f8ff16f67a177c7
DIFF: https://github.com/llvm/llvm-project/commit/78caf4f1bb13c4cf2af3ee9d9f8ff16f67a177c7.diff

LOG: [SchedModels] Limit set of predicates seen by mutuallyExclusive

Patch limits set of predicates seen by mutuallyExclusive to ones which belong
to current processor model. This needs to be done, because same predicate can
be used by multiple processor models which can make mutuallyExclusive over
optimistic.

Added: 
    

Modified: 
    llvm/utils/TableGen/CodeGenSchedule.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/utils/TableGen/CodeGenSchedule.cpp b/llvm/utils/TableGen/CodeGenSchedule.cpp
index 369a3849999f..3ba1b797f6a8 100644
--- a/llvm/utils/TableGen/CodeGenSchedule.cpp
+++ b/llvm/utils/TableGen/CodeGenSchedule.cpp
@@ -1452,10 +1452,15 @@ static bool hasVariant(ArrayRef<PredTransition> Transitions,
   return false;
 }
 
-static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants) {
+static std::vector<Record *> getAllPredicates(ArrayRef<TransVariant> Variants,
+                                              ArrayRef<unsigned> ProcIndices) {
   std::vector<Record *> Preds;
   for (auto &Variant : Variants) {
     assert(Variant.VarOrSeqDef->isSubClassOf("SchedVar"));
+    if (ProcIndices[0] && Variant.ProcIdx)
+      if (!llvm::count(ProcIndices, Variant.ProcIdx))
+        continue;
+
     Preds.push_back(Variant.VarOrSeqDef->getValueAsDef("Predicate"));
   }
   return Preds;
@@ -1507,7 +1512,8 @@ void PredTransitions::getIntersectingVariants(
     if (AliasProcIdx == 0)
       GenericRW = true;
   }
-  std::vector<Record *> AllPreds = getAllPredicates(Variants);
+  std::vector<Record *> AllPreds =
+      getAllPredicates(Variants, TransVec[TransIdx].ProcIndices);
   for (TransVariant &Variant : Variants) {
     // Don't expand variants if the processor models don't intersect.
     // A zero processor index means any processor.