[llvm] 5e9e335 - [GlobalISel][TableGen] Fix seg fault for zero instruction

[Mikael Holmen via llvm-commits]

Author: Gabriel Hjort Åkerlund
Date: 2020-11-24T07:47:58+01:00
New Revision: 5e9e335a247040a175855f99dbab5957064434ba

URL: https://github.com/llvm/llvm-project/commit/5e9e335a247040a175855f99dbab5957064434ba
DIFF: https://github.com/llvm/llvm-project/commit/5e9e335a247040a175855f99dbab5957064434ba.diff

LOG: [GlobalISel][TableGen] Fix seg fault for zero instruction

Tablegen seg faulted when parsing a Pat where the destination part has
no output (zero instruction), due to a register class lookup using
nullptr.

Reviewed By: Paul-C-Anagnostopoulos

Differential Revision: https://reviews.llvm.org/D90829

Added: 
    llvm/test/TableGen/GlobalISelEmitter-zero-instr.td

Modified: 
    llvm/utils/TableGen/GlobalISelEmitter.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td b/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
new file mode 100644
index 000000000000..c8a8cab2b652
--- /dev/null
+++ b/llvm/test/TableGen/GlobalISelEmitter-zero-instr.td
@@ -0,0 +1,8 @@
+// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o /dev/null --warn-on-skipped-patterns 2>&1 < %s 2>&1 | FileCheck %s
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+// CHECK: warning: Skipped pattern: Dst pattern root isn't a known leaf
+def : Pat<(zext (i16 (trunc i32:$src))),
+          (i32 $src)>;

diff  --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index ffd9cf05c124..f81876bc4391 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -5086,9 +5086,9 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
 
   if (Dst->isLeaf()) {
     Record *RCDef = getInitValueAsRegClass(Dst->getLeafValue());
-
-    const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
     if (RCDef) {
+      const CodeGenRegisterClass &RC = Target.getRegisterClass(RCDef);
+
       // We need to replace the def and all its uses with the specified
       // operand. However, we must also insert COPY's wherever needed.
       // For now, emit a copy and let the register allocator clean up.