[PATCH] D91877: [RISCV] Combine GREVI sequences

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1337
+    uint64_t TZ = countTrailingZeros(ShAmt1);
+    if (ShAmt2 != (ShAmt2 & maskTrailingOnes<uint64_t>(TZ)))
+      break;
----------------
craig.topper wrote:
> craig.topper wrote:
> > Does the order matter? Or do we just need (ShAmt1 & ShAmt2) == 0 to hold?
> Maybe we don't even need (ShAmt1 & ShAmt2) == 0  if we XOR the constants. Maybe folding 0 to GREVSrc.
You're right; the order isn't important. Not sure what I was thinking. XORing seems like the best way to go.


Repository:
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  https://reviews.llvm.org/D91877/new/

https://reviews.llvm.org/D91877