[PATCH] D91781: [VE] Add regression test for D91151

Kazushi Marukawa via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 20 21:22:19 PST 2020


kaz7 updated this revision to Diff 306824.
kaz7 added a comment.

Update regression test and rebase it.  Need to inspect behavior of VEISelDAGToDAG.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91781/new/

https://reviews.llvm.org/D91781

Files:
  llvm/test/CodeGen/VE/Scalar/D91151-test.ll


Index: llvm/test/CodeGen/VE/Scalar/D91151-test.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/VE/Scalar/D91151-test.ll
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=ve | FileCheck %s
+
+;; Check that a situation D91151 (https://reviews.llvm.org/D91151) happens.
+
+define i32 @test(i32* %b) {
+; CHECK-LABEL: test
+if.c:
+        %d = load atomic i32, i32* %b monotonic, align 4
+        switch i32 %d, label %e.default [
+                i32 1, label %e.bb
+                i32 2, label %e.f
+                i32 4, label %e.g
+                i32 0, label %if.end
+        ]
+e.bb:
+        br label %if.end
+e.f:
+        br label %if.end
+e.g:
+        br label %if.end
+e.default:
+        br label %if.end
+if.end:
+        %ret.0 = phi i32
+                [ 0, %e.default ],
+                [ 6, %if.c ],
+                [ 0, %e.g ],
+                [ 1, %e.f ],
+                [ 1, %e.bb ]
+        ret i32 %ret.0
+}


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