[PATCH] D91877: [RISCV] Combine GREVI sequences

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1337
+    uint64_t TZ = countTrailingZeros(ShAmt1);
+    if (ShAmt2 != (ShAmt2 & maskTrailingOnes<uint64_t>(TZ)))
+      break;
----------------
Does the order matter? Or do we just need (ShAmt1 & ShAmt2) == 0 to hold?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91877/new/

https://reviews.llvm.org/D91877