[PATCH] D91866: [ARM] Cleanup for the MVETailPrediction pass

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


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Comment at: llvm/lib/Target/ARM/MVETailPredication.cpp:349
   Type *Ty = IntegerType::get(M->getContext(), 32);
-  unsigned VectorWidth = VecTy->getNumElements();
+  unsigned VectorWidth = cast<FixedVectorType>(ActiveLaneMask->getType())->getNumElements();
 
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SjoerdMeijer wrote:
> nit: looks more than 80 columns...
Ah yeah. Will do.


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Comment at: llvm/test/CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll:244
 ; CHECK-NEXT:  .LBB5_1: @ %vector.ph
-; CHECK-NEXT:    adds r3, r2, #3
-; CHECK-NEXT:    vdup.32 q1, r2
-; CHECK-NEXT:    bic r3, r3, #3
-; CHECK-NEXT:    sub.w r12, r3, #4
-; CHECK-NEXT:    movs r3, #1
-; CHECK-NEXT:    add.w lr, r3, r12, lsr #2
-; CHECK-NEXT:    adr r3, .LCPI5_0
-; CHECK-NEXT:    dls lr, lr
-; CHECK-NEXT:    vldrw.u32 q0, [r3]
-; CHECK-NEXT:    mov.w r12, #0
+; CHECK-NEXT:    dlstp.32 lr, r2
 ; CHECK-NEXT:  .LBB5_2: @ %vector.body
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SjoerdMeijer wrote:
> Intially I was expecting this to be a NFC, but looks like it is also doing something good for codegen and we get more tail-predication. Why is that? Is that because of the dead code removal that is no longer in the way?
IsPredicatedVectorLoop would be checking for certain instructions, and only convert the active lane mask if it finds them. This included intrinsics which it did not recognize as vector instructions.

It will always be better to convert to a VCTP than the to expand the active lane mask though, even if the loop does not get tail predicated successfully.

Also, as can be seen in this case, it sometimes gets intrinsics wrong. This is serialized, but that does not block tail predication.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91866/new/

https://reviews.llvm.org/D91866