[PATCH] D91603: [PowerPC] Correct the bit-width definition for some imm operand in td.

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:1900
 
-def DCBF   : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst),
+def DCBF   : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst),
                       "dcbf $dst, $TH", IIC_LdStDCBF, []>,
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qiucf wrote:
> `L` is two bits?
Changed in ISA 3.1 to 3 bits. Bit 8 was reserved before and a value larger than `0b11` had no meaning, so specifying it as 3 bits should be fine.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:2435
 
-def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
+def SYNC : XForm_24_sync<31, 598, (outs), (ins u3imm:$L),
                         "sync $L", IIC_LdStSync, []>;
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qiucf wrote:
> `sync` only uses 2 bits for `L`? (9th-10th bit)
I agree. The instruction format only allows 2 bits in the encoding here. The extra values added in ISA3.0 do not appear to have been used anywhere as doing so would have caused errors.


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  https://reviews.llvm.org/D91603/new/

https://reviews.llvm.org/D91603