[PATCH] D91730: [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.

In D91730#2406401 <https://reviews.llvm.org/D91730#2406401>, @craig.topper wrote:

> In D91730#2405132 <https://reviews.llvm.org/D91730#2405132>, @lenary wrote:
>
>> Is the code change due to the fact that the optimizer later finally knows that `12(sp)` and `8(sp)` don't overlap?
>
> MachineSinking is moving the fld down. It previously couldn't do it because isSafeToMove returned false because hasOrderedMemoryRef() conservatively returned true due to the missing mem operand.
>
>   // a load across an atomic load with Ordering > Monotonic.
>   if (mayStore() || isCall() || isPHI() ||
>       (mayLoad() && hasOrderedMemoryRef())) {
>     SawStore = true;
>     return false;
>   }

Ok, cool, as I thought. Nice patch!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91730/new/

https://reviews.llvm.org/D91730