[PATCH] D91638: [RISCV] Add a proof-of-concept for supporting non-scalable vectors in RVV

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck added a comment.

In D91638#2401155 <https://reviews.llvm.org/D91638#2401155>, @craig.topper wrote:

> This is along the lines of the patch I was working on. I used a new .td file of patterns and started with 64 bit vector types based on the minimum VLEN from Evandro and Roger's RFC.

Makes sense; thanks. Evandro indicated to me that the minimum may become 128 so I jumped on that as it fits OpenCL vectors nicely, but if it's 64 it doesn't change a whole lot.

How concerned are people about this approach? Is it future-proof enough? How big is VLEN going likely to get? Is this too inefficient in terms of register usage?


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