[PATCH] D91848: [AArch64] Enable post RA scheduler for Cortex-R82
Sjoerd Meijer via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 20 02:32:26 PST 2020
SjoerdMeijer updated this revision to Diff 306631.
SjoerdMeijer added a comment.
Thanks Dave, I got so excited about not having to test post RA scheduling I forgot about aes ;-)
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D91848/new/
https://reviews.llvm.org/D91848
Files:
llvm/lib/Target/AArch64/AArch64.td
llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
Index: llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
===================================================================
--- llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
+++ llvm/test/CodeGen/AArch64/misched-fusion-aes.ll
@@ -4,6 +4,7 @@
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 | FileCheck %s
+; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-r82 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s
; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s
Index: llvm/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -670,7 +670,10 @@
def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
"CortexR82",
"Cortex-R82 ARM Processors", [
- // All features are implied by v8_0r ops:
+ FeaturePostRAScheduler,
+ FeatureCrypto,
+ FeatureFuseAES,
+ // All other features are implied by v8_0r ops:
HasV8_0rOps,
]>;
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