[PATCH] D91845: [PowerPC] Fix FLT_ROUNDS_ on little endian

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf created this revision.
qiucf added reviewers: steven.zhang, shchenz, jsji, nemanjai, PowerPC.
Herald added subscribers: llvm-commits, kbarton, hiraditya.
Herald added a project: LLVM.
qiucf requested review of this revision.

Opcode `FLT_ROUNDS_` is lowered as:

1. Move FPSCR content to an FP register
2. Move lower 32 bits into a GPR
3. Adjust its value, and return

For subtargets without direct move support, it will store and then load. The load address needs adjustment (+4) only on big-endian targets. This patch fixes it on little-endian and will try direct move instruction first.


https://reviews.llvm.org/D91845

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/frounds.ll


Index: llvm/test/CodeGen/PowerPC/frounds.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/frounds.ll
+++ llvm/test/CodeGen/PowerPC/frounds.ll
@@ -42,7 +42,7 @@
 ; PPC64LE:       # %bb.0: # %entry
 ; PPC64LE-NEXT:    mffs 0
 ; PPC64LE-NEXT:    stfd 0, -16(1)
-; PPC64LE-NEXT:    lwz 3, -12(1)
+; PPC64LE-NEXT:    lwz 3, -16(1)
 ; PPC64LE-NEXT:    not 4, 3
 ; PPC64LE-NEXT:    clrlwi 3, 3, 30
 ; PPC64LE-NEXT:    rlwinm 4, 4, 31, 31, 31
@@ -54,8 +54,7 @@
 ; DM-LABEL: foo:
 ; DM:       # %bb.0: # %entry
 ; DM-NEXT:    mffs 0
-; DM-NEXT:    stfd 0, -16(1)
-; DM-NEXT:    lwz 3, -12(1)
+; DM-NEXT:    mffprwz 3, 0
 ; DM-NEXT:    not 4, 3
 ; DM-NEXT:    clrlwi 3, 3, 30
 ; DM-NEXT:    rlwinm 4, 4, 31, 31, 31
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8896,16 +8896,24 @@
   SDValue MFFS = DAG.getNode(PPCISD::MFFS, dl, {MVT::f64, MVT::Other}, Chain);
   Chain = MFFS.getValue(1);
 
-  // Save FP register to stack slot
-  int SSFI = MF.getFrameInfo().CreateStackObject(8, Align(8), false);
-  SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
-  Chain = DAG.getStore(Chain, dl, MFFS, StackSlot, MachinePointerInfo());
-
-  // Load FP Control Word from low 32 bits of stack slot.
-  SDValue Four = DAG.getConstant(4, dl, PtrVT);
-  SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
-  SDValue CWD = DAG.getLoad(MVT::i32, dl, Chain, Addr, MachinePointerInfo());
-  Chain = CWD.getValue(1);
+  SDValue CWD;
+  if (Subtarget.hasDirectMove()) {
+    CWD = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, MFFS);
+  } else {
+    // Save FP register to stack slot
+    int SSFI = MF.getFrameInfo().CreateStackObject(8, Align(8), false);
+    SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
+    Chain = DAG.getStore(Chain, dl, MFFS, StackSlot, MachinePointerInfo());
+
+    // Load FP Control Word from low 32 bits of stack slot.
+    SDValue Addr = StackSlot;
+    if (!Subtarget.isLittleEndian()) {
+      SDValue Four = DAG.getConstant(4, dl, PtrVT);
+      Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
+    }
+    CWD = DAG.getLoad(MVT::i32, dl, Chain, Addr, MachinePointerInfo());
+    Chain = CWD.getValue(1);
+  }
 
   // Transform as necessary
   SDValue CWD1 =


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