[llvm] 8ecb015 - [ARM][LowOverheadLoops] Convert intermediate vpr use assertion to condition
Sam Tebbs via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 19 09:15:54 PST 2020
Author: Sam Tebbs
Date: 2020-11-19T17:15:45Z
New Revision: 8ecb015ed5ad635f5faccd5303e53dd759a56447
URL: https://github.com/llvm/llvm-project/commit/8ecb015ed5ad635f5faccd5303e53dd759a56447
DIFF: https://github.com/llvm/llvm-project/commit/8ecb015ed5ad635f5faccd5303e53dd759a56447.diff
LOG: [ARM][LowOverheadLoops] Convert intermediate vpr use assertion to condition
This converts the intermediate VPR use assertion to a condition in the if-statement to protect against assertion failures in case behaviuour is changed.
This is a follow-up to https://reviews.llvm.org/D90935 and implements the post-approval comments.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D91790
Added:
Modified:
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index 9f6f6d03aad5..0f0418901bec 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -1575,16 +1575,14 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
!LoLoop.ToRemove.contains(VprDef)) {
MachineInstr *VCMP = VprDef;
// The VCMP and VPST can only be merged if the VCMP's operands will have
- // the same values at the VPST
- if (RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(1).getReg()) &&
+ // the same values at the VPST.
+ // If any of the instructions between the VCMP and VPST are predicated
+ // then a
diff erent code path is expected to have merged the VCMP and
+ // VPST already.
+ if (!std::any_of(++MachineBasicBlock::iterator(VCMP),
+ MachineBasicBlock::iterator(VPST), hasVPRUse) &&
+ RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(1).getReg()) &&
RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(2).getReg())) {
- // If the instruction after the VCMP is predicated then a
diff erent
- // code path is expected to have merged the VCMP and VPST already.
- // This assertion protects against changes to that behaviour
- assert(!std::any_of(++MachineBasicBlock::iterator(VCMP),
- MachineBasicBlock::iterator(VPST), hasVPRUse) &&
- "Instructions between the VCMP and VPST are not expected to "
- "be predicated");
ReplaceVCMPWithVPT(VCMP, VPST);
LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
LoLoop.ToRemove.insert(VPST);
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir
index 0ed94da7d2a4..159a89497c6a 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir
@@ -17,6 +17,11 @@
ret void
}
+ define void @combine_kill_flags() {
+ while.end6:
+ ret void
+ }
+
define void @no_combination_
diff _reg_value() {
while.end6:
ret void
@@ -162,7 +167,7 @@ body: |
; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q2
; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
- ; CHECK: MVE_VPST 4, implicit $vpr
+ ; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2:
@@ -194,7 +199,7 @@ body: |
renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
MVE_VPST 8, implicit $vpr
renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
- MVE_VPST 4, implicit $vpr
+ MVE_VPST 8, implicit $vpr
renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
tB %bb.8, 14 /* CC::al */, $noreg
@@ -296,6 +301,93 @@ body: |
bb.9 (align 4):
CONSTPOOL_ENTRY 0, %const.0, 4
+...
+---
+name: combine_kill_flags
+alignment: 8
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+debugValueSubstitutions: []
+constants:
+ - id: 0
+ value: float 0xC7EFFFFFE0000000
+ alignment: 4
+ isTargetSpecific: false
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: combine_kill_flags
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $q2, $r0, $r1
+ ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
+ ; CHECK: bb.1 (align 4):
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $q2, $r0
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
+ ; CHECK: renamable $q2 = MVE_VORR killed renamable $q2, renamable $q1, 0, $noreg, killed renamable $q2
+ ; CHECK: MVE_VPTv4f32 8, renamable $q0, killed renamable $q1, 12, implicit-def $vpr
+ ; CHECK: renamable $q0 = MVE_VORR killed renamable $q0, killed renamable $q0, 1, killed renamable $vpr, killed renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK: bb.2:
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+ ; CHECK: bb.3 (align 4):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
+ bb.0:
+ successors: %bb.6(0x80000000)
+ liveins: $r0, $r1, $r2
+
+ renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
+ renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
+ $lr = t2DoLoopStart renamable $lr
+
+ bb.6 (align 4):
+ successors: %bb.6(0x7c000000), %bb.8(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2, $q2
+
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
+ renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
+ MVE_VPST 2, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
+ renamable $vpr = MVE_VCMPf32 renamable $q0, renamable $q1, 12, 1, killed renamable $vpr
+ renamable $q2 = MVE_VORR renamable $q2, killed renamable $q1, 0, $noreg, killed renamable $q2
+ MVE_VPST 8, implicit $vpr
+ renamable $q0 = MVE_VORR renamable $q0, renamable $q0, 1, renamable $vpr, killed renamable $q0
+ t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
+ tB %bb.8, 14 /* CC::al */, $noreg
+
+ bb.8:
+ liveins: $r2, $r12, $q0
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+ bb.9 (align 4):
+ CONSTPOOL_ENTRY 0, %const.0, 4
+
...
---
name: no_combination_
diff _reg_value
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