[PATCH] D91790: [ARM][LowOverheadLoops] Convert intermediate vpr use assertion to condition

[Sam Tebbs via Phabricator via llvm-commits]

samtebbs updated this revision to Diff 306425.
samtebbs added a comment.

Fix test ordering. This is an NFC so I will commit with the previous approval.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91790/new/

https://reviews.llvm.org/D91790

Files:
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D91790.306425.patch
Type: text/x-patch
Size: 7372 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201119/ae907083/attachment.bin>