[llvm] a1de391 - [LV][NFC-ish] Allow vector widths over 256 elements

[Simon Moll via llvm-commits]

Author: Simon Moll
Date: 2020-11-19T10:58:29+01:00
New Revision: a1de391dae8b6851c49a54da984c19d556c2b561

URL: https://github.com/llvm/llvm-project/commit/a1de391dae8b6851c49a54da984c19d556c2b561
DIFF: https://github.com/llvm/llvm-project/commit/a1de391dae8b6851c49a54da984c19d556c2b561.diff

LOG: [LV][NFC-ish] Allow vector widths over 256 elements

The assertion that vector widths are <= 256 elements was hard wired in the LV code. Eg, VE allows for vectors up to 512 elements. Test again the TTI vector register bit width instead - this is an NFC for non-asserting builds.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D91518

Added: 
    

Modified: 
    llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Removed: 
    


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diff  --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 8376bd2ce9e6..75ecb505b985 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5349,8 +5349,9 @@ LoopVectorizationCostModel::computeFeasibleMaxVF(unsigned ConstTripCount) {
   LLVM_DEBUG(dbgs() << "LV: The Widest register safe to use is: "
                     << WidestRegister << " bits.\n");
 
-  assert(MaxVectorSize <= 256 && "Did not expect to pack so many elements"
-                                 " into one vector!");
+  assert(MaxVectorSize <= WidestRegister &&
+         "Did not expect to pack so many elements"
+         " into one vector!");
   if (MaxVectorSize == 0) {
     LLVM_DEBUG(dbgs() << "LV: The target has no vector registers.\n");
     MaxVectorSize = 1;