[PATCH] D91710: [SelDAGBuilder] Do not require simple VTs for constraints.

[Florian Hahn via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1983acce7c4d: [SelDAGBuilder] Do not require simple VTs for constraints. (authored by fhahn).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91710/new/

https://reviews.llvm.org/D91710

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
  llvm/test/CodeGen/AArch64/inlineasm-illegal-type.ll


Index: llvm/test/CodeGen/AArch64/inlineasm-illegal-type.ll
===================================================================
--- llvm/test/CodeGen/AArch64/inlineasm-illegal-type.ll
+++ llvm/test/CodeGen/AArch64/inlineasm-illegal-type.ll
@@ -2,6 +2,8 @@
 
 ; CHECK: error: couldn't allocate output register for constraint '{d0}'
 ; CHECK: error: couldn't allocate output register for constraint 'w'
+; CHECK: error: couldn't allocate input reg for constraint 'w'
+; CHECK: error: couldn't allocate input reg for constraint 'w'
 
 define hidden double @test1(double %xx) local_unnamed_addr #0 {
 entry:
@@ -15,3 +17,16 @@
   ret double %0
 }
 
+define void @test_vector_too_large(<8 x float>* nocapture readonly %0) {
+entry:
+  %m = load <8 x float>, <8 x float>* %0, align 16
+  tail call void asm sideeffect "fadd.4s v4, v4, $0", "w,~{memory}"(<8 x float> %m)
+  ret void
+}
+
+define void @test_vector_no_mvt(<9 x float>* nocapture readonly %0) {
+entry:
+  %m = load <9 x float>, <9 x float>* %0, align 16
+  tail call void asm sideeffect "fadd.4s v4, v4, $0", "w,~{memory}"(<9 x float> %m)
+  ret void
+}
Index: llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
+++ llvm/test/CodeGen/AArch64/arm64-inline-asm.ll
@@ -282,3 +282,18 @@
   tail call void asm sideeffect "fmla v2.4s, v0.4s, v1.s[$0]", "I"(i32 1) #1
   ret void
 }
+define void @test_vector_too_large_r_m(<9 x float>* nocapture readonly %0) {
+; CHECK-LABEL: test_vector_too_large_r_m
+; CHECK:      ldr [[S:s[0-9]+]], [x0, #32]
+; CHECK-DAG:  ldp [[Q0:q[0-9]+]], [[Q1:q[0-9]+]], [x0]
+; CHECK:      str [[S]], [sp, #32]
+; CHECK-DAG   stp [[Q0]], [[Q1]], [sp]
+; CHECK:     ; InlineAsm Start
+;
+entry:
+  %m.addr = alloca <9 x float>, align 16
+  %m = load <9 x float>, <9 x float>* %0, align 16
+  store <9 x float> %m, <9 x float>* %m.addr, align 16
+  call void asm sideeffect "", "=*r|m,0,~{memory}"(<9 x float>* nonnull %m.addr, <9 x float> %m)
+  ret void
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -8087,10 +8087,9 @@
         OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
       }
 
-      OpInfo.ConstraintVT =
-          OpInfo
-              .getCallOperandValEVT(*DAG.getContext(), TLI, DAG.getDataLayout())
-              .getSimpleVT();
+      EVT VT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI,
+                                           DAG.getDataLayout());
+      OpInfo.ConstraintVT = VT.isSimple() ? VT.getSimpleVT() : MVT::Other;
     } else if (OpInfo.Type == InlineAsm::isOutput && !OpInfo.isIndirect) {
       // The return value of the call is this value.  As such, there is no
       // corresponding argument.


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