[llvm] 6b0fc1f - [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 18 19:22:27 PST 2020
Author: Craig Topper
Date: 2020-11-18T19:20:03-08:00
New Revision: 6b0fc1f3c161295e6577d4c2237cefcb8e4dd9ba
URL: https://github.com/llvm/llvm-project/commit/6b0fc1f3c161295e6577d4c2237cefcb8e4dd9ba
DIFF: https://github.com/llvm/llvm-project/commit/6b0fc1f3c161295e6577d4c2237cefcb8e4dd9ba.diff
LOG: [RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot
Differential Revision: https://reviews.llvm.org/D91730
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 1672b17df966..084298685672 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -119,8 +119,13 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
if (I != MBB.end())
DL = I->getDebugLoc();
- unsigned Opcode;
+ MachineFunction *MF = MBB.getParent();
+ const MachineFrameInfo &MFI = MF->getFrameInfo();
+ MachineMemOperand *MMO = MF->getMachineMemOperand(
+ MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore,
+ MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
+ unsigned Opcode;
if (RISCV::GPRRegClass.hasSubClassEq(RC))
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
RISCV::SW : RISCV::SD;
@@ -134,7 +139,8 @@ void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
BuildMI(MBB, I, DL, get(Opcode))
.addReg(SrcReg, getKillRegState(IsKill))
.addFrameIndex(FI)
- .addImm(0);
+ .addImm(0)
+ .addMemOperand(MMO);
}
void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -146,8 +152,13 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
if (I != MBB.end())
DL = I->getDebugLoc();
- unsigned Opcode;
+ MachineFunction *MF = MBB.getParent();
+ const MachineFrameInfo &MFI = MF->getFrameInfo();
+ MachineMemOperand *MMO = MF->getMachineMemOperand(
+ MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad,
+ MFI.getObjectSize(FI), MFI.getObjectAlign(FI));
+ unsigned Opcode;
if (RISCV::GPRRegClass.hasSubClassEq(RC))
Opcode = TRI->getRegSizeInBits(RISCV::GPRRegClass) == 32 ?
RISCV::LW : RISCV::LD;
@@ -158,7 +169,10 @@ void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
else
llvm_unreachable("Can't load this register from stack slot");
- BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
+ BuildMI(MBB, I, DL, get(Opcode), DstReg)
+ .addFrameIndex(FI)
+ .addImm(0)
+ .addMemOperand(MMO);
}
void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
index 9813df4fbb85..5dbaa90e4698 100644
--- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
+++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll
@@ -222,14 +222,13 @@ define double @cmovdouble(i1 %a, double %b, double %c) nounwind {
; RV32I-NEXT: sw a4, 12(sp)
; RV32I-NEXT: fld ft0, 8(sp)
; RV32I-NEXT: sw a1, 8(sp)
-; RV32I-NEXT: sw a2, 12(sp)
-; RV32I-NEXT: fld ft1, 8(sp)
; RV32I-NEXT: andi a0, a0, 1
-; RV32I-NEXT: bnez a0, .LBB5_2
-; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: fmv.d ft1, ft0
+; RV32I-NEXT: sw a2, 12(sp)
+; RV32I-NEXT: beqz a0, .LBB5_2
+; RV32I-NEXT: # %bb.1:
+; RV32I-NEXT: fld ft0, 8(sp)
; RV32I-NEXT: .LBB5_2: # %entry
-; RV32I-NEXT: fsd ft1, 8(sp)
+; RV32I-NEXT: fsd ft0, 8(sp)
; RV32I-NEXT: lw a0, 8(sp)
; RV32I-NEXT: lw a1, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
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