[llvm] 06fcc4f - [NFC] Use [MC]Register for Hexagon target
Gaurav Jain via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 18 08:19:51 PST 2020
Author: Gaurav Jain
Date: 2020-11-18T08:17:07-08:00
New Revision: 06fcc4f06f1401d6fa47759f282efdc7f494999f
URL: https://github.com/llvm/llvm-project/commit/06fcc4f06f1401d6fa47759f282efdc7f494999f
DIFF: https://github.com/llvm/llvm-project/commit/06fcc4f06f1401d6fa47759f282efdc7f494999f.diff
LOG: [NFC] Use [MC]Register for Hexagon target
Differential Revision: https://reviews.llvm.org/D91160
Added:
Modified:
llvm/lib/Target/Hexagon/BitTracker.cpp
llvm/lib/Target/Hexagon/BitTracker.h
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
llvm/lib/Target/Hexagon/HexagonBitTracker.h
llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
llvm/lib/Target/Hexagon/HexagonBlockRanges.h
llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/lib/Target/Hexagon/HexagonPeephole.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index 7ef23ef35a74..d9cb64824168 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -198,10 +198,10 @@ BitTracker::~BitTracker() {
// the actual bits of the "self" register.
// While this cannot happen in the current implementation, I'm not sure
// if this should be ruled out in the future.
-bool BT::RegisterCell::meet(const RegisterCell &RC, unsigned SelfR) {
+bool BT::RegisterCell::meet(const RegisterCell &RC, Register SelfR) {
// An example when "meet" can be invoked with SelfR == 0 is a phi node
// with a physical register as an operand.
- assert(SelfR == 0 || Register::isVirtualRegister(SelfR));
+ assert(SelfR == 0 || SelfR.isVirtual());
bool Changed = false;
for (uint16_t i = 0, n = Bits.size(); i < n; ++i) {
const BitValue &RCV = RC[i];
@@ -335,11 +335,11 @@ uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const {
// 1. find a physical register PhysR from the same class as RR.Reg,
// 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
// 3. find a register class that contains PhysS.
- if (Register::isVirtualRegister(RR.Reg)) {
+ if (RR.Reg.isVirtual()) {
const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
return TRI.getRegSizeInBits(VC);
}
- assert(Register::isPhysicalRegister(RR.Reg));
+ assert(RR.Reg.isPhysical());
Register PhysR =
(RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub);
return getPhysRegBitWidth(PhysR);
@@ -351,10 +351,10 @@ BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR,
// Physical registers are assumed to be present in the map with an unknown
// value. Don't actually insert anything in the map, just return the cell.
- if (Register::isPhysicalRegister(RR.Reg))
+ if (RR.Reg.isPhysical())
return RegisterCell::self(0, BW);
- assert(Register::isVirtualRegister(RR.Reg));
+ assert(RR.Reg.isVirtual());
// For virtual registers that belong to a class that is not tracked,
// generate an "unknown" value as well.
const TargetRegisterClass *C = MRI.getRegClass(RR.Reg);
@@ -377,7 +377,7 @@ void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC,
// While updating the cell map can be done in a meaningful way for
// a part of a register, it makes little sense to implement it as the
// SSA representation would never contain such "partial definitions".
- if (!Register::isVirtualRegister(RR.Reg))
+ if (!RR.Reg.isVirtual())
return;
assert(RR.Sub == 0 && "Unexpected sub-register in definition");
// Eliminate all ref-to-reg-0 bit values: replace them with "self".
@@ -704,15 +704,15 @@ BT::RegisterCell BT::MachineEvaluator::eINS(const RegisterCell &A1,
return Res;
}
-BT::BitMask BT::MachineEvaluator::mask(unsigned Reg, unsigned Sub) const {
+BT::BitMask BT::MachineEvaluator::mask(Register Reg, unsigned Sub) const {
assert(Sub == 0 && "Generic BitTracker::mask called for Sub != 0");
uint16_t W = getRegBitWidth(Reg);
assert(W > 0 && "Cannot generate mask for empty register");
return BitMask(0, W-1);
}
-uint16_t BT::MachineEvaluator::getPhysRegBitWidth(unsigned Reg) const {
- assert(Register::isPhysicalRegister(Reg));
+uint16_t BT::MachineEvaluator::getPhysRegBitWidth(Register Reg) const {
+ assert(Reg.isPhysical());
const TargetRegisterClass &PC = *TRI.getMinimalPhysRegClass(Reg);
return TRI.getRegSizeInBits(PC);
}
@@ -875,7 +875,7 @@ void BT::visitNonBranch(const MachineInstr &MI) {
continue;
RegisterRef RD(MO);
assert(RD.Sub == 0 && "Unexpected sub-register in definition");
- if (!Register::isVirtualRegister(RD.Reg))
+ if (!RD.Reg.isVirtual())
continue;
bool Changed = false;
@@ -980,7 +980,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
FlowQ.push(CFGEdge(ThisN, TB->getNumber()));
}
-void BT::visitUsesOf(unsigned Reg) {
+void BT::visitUsesOf(Register Reg) {
if (Trace)
dbgs() << "queuing uses of modified reg " << printReg(Reg, &ME.TRI)
<< " cell: " << ME.getCell(Reg, Map) << '\n';
diff --git a/llvm/lib/Target/Hexagon/BitTracker.h b/llvm/lib/Target/Hexagon/BitTracker.h
index efb21805b801..9c42fc670610 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.h
+++ b/llvm/lib/Target/Hexagon/BitTracker.h
@@ -62,7 +62,7 @@ struct BitTracker {
void visitPHI(const MachineInstr &PI);
void visitNonBranch(const MachineInstr &MI);
void visitBranchesFrom(const MachineInstr &BI);
- void visitUsesOf(unsigned Reg);
+ void visitUsesOf(Register Reg);
using CFGEdge = std::pair<int, int>;
using EdgeSetType = std::set<CFGEdge>;
@@ -131,19 +131,20 @@ struct BitTracker::BitRef {
return Reg == BR.Reg && (Reg == 0 || Pos == BR.Pos);
}
- unsigned Reg;
+ Register Reg;
uint16_t Pos;
};
// Abstraction of a register reference in MachineOperand. It contains the
// register number and the subregister index.
+// FIXME: Consolidate duplicate definitions of RegisterRef
struct BitTracker::RegisterRef {
- RegisterRef(unsigned R = 0, unsigned S = 0)
- : Reg(R), Sub(S) {}
+ RegisterRef(Register R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
RegisterRef(const MachineOperand &MO)
: Reg(MO.getReg()), Sub(MO.getSubReg()) {}
- unsigned Reg, Sub;
+ Register Reg;
+ unsigned Sub;
};
// Value that a single bit can take. This is outside of the context of
@@ -312,7 +313,7 @@ struct BitTracker::RegisterCell {
return Bits[BitN];
}
- bool meet(const RegisterCell &RC, unsigned SelfR);
+ bool meet(const RegisterCell &RC, Register SelfR);
RegisterCell &insert(const RegisterCell &RC, const BitMask &M);
RegisterCell extract(const BitMask &M) const; // Returns a new cell.
RegisterCell &rol(uint16_t Sh); // Rotate left.
@@ -461,7 +462,7 @@ struct BitTracker::MachineEvaluator {
// Sub == 0, in this case, the function should return a mask that spans
// the entire register Reg (which is what the default implementation
// does).
- virtual BitMask mask(unsigned Reg, unsigned Sub) const;
+ virtual BitMask mask(Register Reg, unsigned Sub) const;
// Indicate whether a given register class should be tracked.
virtual bool track(const TargetRegisterClass *RC) const { return true; }
// Evaluate a non-branching machine instruction, given the cell map with
@@ -484,7 +485,7 @@ struct BitTracker::MachineEvaluator {
llvm_unreachable("Unimplemented composeWithSubRegIndex");
}
// Return the size in bits of the physical register Reg.
- virtual uint16_t getPhysRegBitWidth(unsigned Reg) const;
+ virtual uint16_t getPhysRegBitWidth(Register Reg) const;
const TargetRegisterInfo &TRI;
MachineRegisterInfo &MRI;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 49edb0d99492..54aa14849dd9 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -206,14 +206,14 @@ namespace {
uint16_t W);
static bool getConst(const BitTracker::RegisterCell &RC, uint16_t B,
uint16_t W, uint64_t &U);
- static bool replaceReg(unsigned OldR, unsigned NewR,
- MachineRegisterInfo &MRI);
+ static bool replaceReg(Register OldR, Register NewR,
+ MachineRegisterInfo &MRI);
static bool getSubregMask(const BitTracker::RegisterRef &RR,
unsigned &Begin, unsigned &Width, MachineRegisterInfo &MRI);
- static bool replaceRegWithSub(unsigned OldR, unsigned NewR,
- unsigned NewSR, MachineRegisterInfo &MRI);
- static bool replaceSubWithSub(unsigned OldR, unsigned OldSR,
- unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI);
+ static bool replaceRegWithSub(Register OldR, Register NewR, unsigned NewSR,
+ MachineRegisterInfo &MRI);
+ static bool replaceSubWithSub(Register OldR, unsigned OldSR, Register NewR,
+ unsigned NewSR, MachineRegisterInfo &MRI);
static bool parseRegSequence(const MachineInstr &I,
BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH,
const MachineRegisterInfo &MRI);
@@ -292,7 +292,7 @@ void HexagonBitSimplify::getInstrDefs(const MachineInstr &MI,
if (!Op.isReg() || !Op.isDef())
continue;
Register R = Op.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
Defs.insert(R);
}
@@ -304,7 +304,7 @@ void HexagonBitSimplify::getInstrUses(const MachineInstr &MI,
if (!Op.isReg() || !Op.isUse())
continue;
Register R = Op.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
Uses.insert(R);
}
@@ -352,9 +352,9 @@ bool HexagonBitSimplify::getConst(const BitTracker::RegisterCell &RC,
return true;
}
-bool HexagonBitSimplify::replaceReg(unsigned OldR, unsigned NewR,
- MachineRegisterInfo &MRI) {
- if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
+bool HexagonBitSimplify::replaceReg(Register OldR, Register NewR,
+ MachineRegisterInfo &MRI) {
+ if (!OldR.isVirtual() || !NewR.isVirtual())
return false;
auto Begin = MRI.use_begin(OldR), End = MRI.use_end();
decltype(End) NextI;
@@ -365,9 +365,10 @@ bool HexagonBitSimplify::replaceReg(unsigned OldR, unsigned NewR,
return Begin != End;
}
-bool HexagonBitSimplify::replaceRegWithSub(unsigned OldR, unsigned NewR,
- unsigned NewSR, MachineRegisterInfo &MRI) {
- if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
+bool HexagonBitSimplify::replaceRegWithSub(Register OldR, Register NewR,
+ unsigned NewSR,
+ MachineRegisterInfo &MRI) {
+ if (!OldR.isVirtual() || !NewR.isVirtual())
return false;
if (hasTiedUse(OldR, MRI, NewSR))
return false;
@@ -381,9 +382,10 @@ bool HexagonBitSimplify::replaceRegWithSub(unsigned OldR, unsigned NewR,
return Begin != End;
}
-bool HexagonBitSimplify::replaceSubWithSub(unsigned OldR, unsigned OldSR,
- unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI) {
- if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
+bool HexagonBitSimplify::replaceSubWithSub(Register OldR, unsigned OldSR,
+ Register NewR, unsigned NewSR,
+ MachineRegisterInfo &MRI) {
+ if (!OldR.isVirtual() || !NewR.isVirtual())
return false;
if (OldSR != NewSR && hasTiedUse(OldR, MRI, NewSR))
return false;
@@ -894,7 +896,7 @@ bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN,
// register class.
const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
- if (!Register::isVirtualRegister(RR.Reg))
+ if (!RR.Reg.isVirtual())
return nullptr;
auto *RC = MRI.getRegClass(RR.Reg);
if (RR.Sub == 0)
@@ -925,8 +927,7 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
// with a 32-bit register.
bool HexagonBitSimplify::isTransparentCopy(const BitTracker::RegisterRef &RD,
const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) {
- if (!Register::isVirtualRegister(RD.Reg) ||
- !Register::isVirtualRegister(RS.Reg))
+ if (!RD.Reg.isVirtual() || !RS.Reg.isVirtual())
return false;
// Return false if one (or both) classes are nullptr.
auto *DRC = getFinalVRegClass(RD, MRI);
@@ -1017,7 +1018,7 @@ bool DeadCodeElimination::runOnNode(MachineDomTreeNode *N) {
if (!Op.isReg() || !Op.isDef())
continue;
Register R = Op.getReg();
- if (!Register::isVirtualRegister(R) || !isDead(R)) {
+ if (!R.isVirtual() || !isDead(R)) {
AllDead = false;
break;
}
@@ -1219,7 +1220,7 @@ bool RedundantInstrElimination::computeUsedBits(unsigned Reg, BitVector &Bits) {
MachineInstr &UseI = *I->getParent();
if (UseI.isPHI() || UseI.isCopy()) {
Register DefR = UseI.getOperand(0).getReg();
- if (!Register::isVirtualRegister(DefR))
+ if (!DefR.isVirtual())
return false;
Pending.push_back(DefR);
} else {
@@ -1380,8 +1381,9 @@ namespace {
static bool isTfrConst(const MachineInstr &MI);
private:
- unsigned genTfrConst(const TargetRegisterClass *RC, int64_t C,
- MachineBasicBlock &B, MachineBasicBlock::iterator At, DebugLoc &DL);
+ Register genTfrConst(const TargetRegisterClass *RC, int64_t C,
+ MachineBasicBlock &B, MachineBasicBlock::iterator At,
+ DebugLoc &DL);
const HexagonInstrInfo &HII;
MachineRegisterInfo &MRI;
@@ -1408,8 +1410,10 @@ bool ConstGeneration::isTfrConst(const MachineInstr &MI) {
// Generate a transfer-immediate instruction that is appropriate for the
// register class and the actual value being transferred.
-unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C,
- MachineBasicBlock &B, MachineBasicBlock::iterator At, DebugLoc &DL) {
+Register ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C,
+ MachineBasicBlock &B,
+ MachineBasicBlock::iterator At,
+ DebugLoc &DL) {
Register Reg = MRI.createVirtualRegister(RC);
if (RC == &Hexagon::IntRegsRegClass) {
BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), Reg)
@@ -1473,8 +1477,8 @@ bool ConstGeneration::processBlock(MachineBasicBlock &B, const RegisterSet&) {
HBS::getInstrDefs(*I, Defs);
if (Defs.count() != 1)
continue;
- unsigned DR = Defs.find_first();
- if (!Register::isVirtualRegister(DR))
+ Register DR = Defs.find_first();
+ if (!DR.isVirtual())
continue;
uint64_t U;
const BitTracker::RegisterCell &DRC = BT.lookup(DR);
@@ -1482,7 +1486,7 @@ bool ConstGeneration::processBlock(MachineBasicBlock &B, const RegisterSet&) {
int64_t C = U;
DebugLoc DL = I->getDebugLoc();
auto At = I->isPHI() ? B.getFirstNonPHI() : I;
- unsigned ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL);
+ Register ImmReg = genTfrConst(MRI.getRegClass(DR), C, B, At, DL);
if (ImmReg) {
HBS::replaceReg(DR, ImmReg, MRI);
BT.put(ImmReg, DRC);
@@ -1549,7 +1553,7 @@ bool CopyGeneration::findMatch(const BitTracker::RegisterRef &Inp,
if (!HBS::getSubregMask(Inp, B, W, MRI))
return false;
- for (unsigned R = AVs.find_first(); R; R = AVs.find_next(R)) {
+ for (Register R = AVs.find_first(); R; R = AVs.find_next(R)) {
if (!BT.has(R) || Forbidden[R])
continue;
const BitTracker::RegisterCell &RC = BT.lookup(R);
@@ -1608,7 +1612,7 @@ bool CopyGeneration::processBlock(MachineBasicBlock &B,
DebugLoc DL = I->getDebugLoc();
auto At = I->isPHI() ? B.getFirstNonPHI() : I;
- for (unsigned R = Defs.find_first(); R; R = Defs.find_next(R)) {
+ for (Register R = Defs.find_first(); R; R = Defs.find_next(R)) {
BitTracker::RegisterRef MR;
auto *FRC = HBS::getFinalVRegClass(R, MRI);
@@ -1815,7 +1819,7 @@ bool BitSimplification::matchHalf(unsigned SelfR,
if (I == B+16)
return false;
- unsigned Reg = RC[I].RefI.Reg;
+ Register Reg = RC[I].RefI.Reg;
unsigned P = RC[I].RefI.Pos; // The RefI.Pos will be advanced by I-B.
if (P < I-B)
return false;
@@ -1823,7 +1827,7 @@ bool BitSimplification::matchHalf(unsigned SelfR,
if (Reg == 0 || Reg == SelfR) // Don't match "self".
return false;
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
return false;
if (!BT.has(Reg))
return false;
@@ -2363,7 +2367,7 @@ bool BitSimplification::simplifyTstbit(MachineInstr *MI,
P = V.RefI.Pos;
}
if (P != std::numeric_limits<unsigned>::max()) {
- unsigned NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
+ Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass);
BuildMI(B, At, DL, HII.get(Hexagon::S2_tstbit_i), NewR)
.addReg(RR.Reg, 0, RR.Sub)
.addImm(P);
@@ -3165,8 +3169,8 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
HBS::getInstrDefs(*I, Defs);
if (Defs.count() != 1)
continue;
- unsigned DefR = Defs.find_first();
- if (!Register::isVirtualRegister(DefR))
+ Register DefR = Defs.find_first();
+ if (!DefR.isVirtual())
continue;
if (!isBitShuffle(&*I, DefR))
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index 1e4030b84bc1..de24c8496c1e 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -86,7 +86,7 @@ HexagonEvaluator::HexagonEvaluator(const HexagonRegisterInfo &tri,
}
}
-BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
+BT::BitMask HexagonEvaluator::mask(Register Reg, unsigned Sub) const {
if (Sub == 0)
return MachineEvaluator::mask(Reg, 0);
const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
@@ -110,8 +110,8 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
llvm_unreachable("Unexpected register/subregister");
}
-uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
- assert(Register::isPhysicalRegister(Reg));
+uint16_t HexagonEvaluator::getPhysRegBitWidth(Register Reg) const {
+ assert(Reg.isPhysical());
using namespace Hexagon;
const auto &HST = MF.getSubtarget<HexagonSubtarget>();
@@ -1043,7 +1043,7 @@ unsigned HexagonEvaluator::getUniqueDefVReg(const MachineInstr &MI) const {
if (!Op.isReg() || !Op.isDef())
continue;
Register R = Op.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
if (DefReg != 0)
return 0;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.h b/llvm/lib/Target/Hexagon/HexagonBitTracker.h
index 02607d50f686..dc2f141ef509 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.h
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.h
@@ -36,9 +36,9 @@ struct HexagonEvaluator : public BitTracker::MachineEvaluator {
bool evaluate(const MachineInstr &BI, const CellMapType &Inputs,
BranchTargetList &Targets, bool &FallsThru) const override;
- BitTracker::BitMask mask(unsigned Reg, unsigned Sub) const override;
+ BitTracker::BitMask mask(Register Reg, unsigned Sub) const override;
- uint16_t getPhysRegBitWidth(unsigned Reg) const override;
+ uint16_t getPhysRegBitWidth(Register Reg) const override;
const TargetRegisterClass &composeWithSubRegIndex(
const TargetRegisterClass &RC, unsigned Idx) const override;
diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
index d1d1b8ee7d41..1f49e0d14de9 100644
--- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
@@ -275,7 +275,7 @@ HexagonBlockRanges::RegisterSet HexagonBlockRanges::expandToSubRegs(
for (; I.isValid(); ++I)
SRs.insert({*I, 0});
} else {
- assert(Register::isVirtualRegister(R.Reg));
+ assert(R.Reg.isVirtual());
auto &RC = *MRI.getRegClass(R.Reg);
unsigned PReg = *RC.begin();
MCSubRegIndexIterator I(PReg, &TRI);
@@ -482,7 +482,7 @@ HexagonBlockRanges::RegToRangeMap HexagonBlockRanges::computeDeadMap(
}
}
for (auto &P : LiveMap)
- if (Register::isVirtualRegister(P.first.Reg))
+ if (P.first.Reg.isVirtual())
addDeadRanges(P.first);
LLVM_DEBUG(dbgs() << __func__ << ": dead map\n"
diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.h b/llvm/lib/Target/Hexagon/HexagonBlockRanges.h
index 61115e29a708..5a3b6433fba7 100644
--- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.h
+++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.h
@@ -10,6 +10,7 @@
#define LLVM_LIB_TARGET_HEXAGON_HEXAGONBLOCKRANGES_H
#include "llvm/ADT/BitVector.h"
+#include "llvm/CodeGen/Register.h"
#include <cassert>
#include <map>
#include <set>
@@ -30,8 +31,10 @@ class TargetRegisterInfo;
struct HexagonBlockRanges {
HexagonBlockRanges(MachineFunction &MF);
+ // FIXME: Consolidate duplicate definitions of RegisterRef
struct RegisterRef {
- unsigned Reg, Sub;
+ llvm::Register Reg;
+ unsigned Sub;
bool operator<(RegisterRef R) const {
return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
index 05b95d8b7314..a774baaa48e6 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -242,18 +242,15 @@ namespace {
return *this;
}
bool isVReg() const {
- return Reg != 0 && !llvm::Register::isStackSlot(Reg) &&
- llvm::Register::isVirtualRegister(Reg);
- }
- bool isSlot() const {
- return Reg != 0 && llvm::Register::isStackSlot(Reg);
+ return Reg != 0 && !Reg.isStack() && Reg.isVirtual();
}
+ bool isSlot() const { return Reg != 0 && Reg.isStack(); }
operator MachineOperand() const {
if (isVReg())
return MachineOperand::CreateReg(Reg, /*Def*/false, /*Imp*/false,
/*Kill*/false, /*Dead*/false, /*Undef*/false,
/*EarlyClobber*/false, Sub);
- if (llvm::Register::isStackSlot(Reg)) {
+ if (Reg.isStack()) {
int FI = llvm::Register::stackSlot2Index(Reg);
return MachineOperand::CreateFI(FI);
}
@@ -265,7 +262,8 @@ namespace {
// For std::map.
return Reg < R.Reg || (Reg == R.Reg && Sub < R.Sub);
}
- unsigned Reg = 0, Sub = 0;
+ llvm::Register Reg;
+ unsigned Sub = 0;
};
struct ExtExpr {
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index 77578378b058..4a2b0600f42b 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -83,7 +83,8 @@ namespace {
// FIXME: Use TargetInstrInfo::RegSubRegPair. Also duplicated in
// HexagonGenPredicate
struct RegisterSubReg {
- unsigned Reg, SubReg;
+ Register Reg;
+ unsigned SubReg;
explicit RegisterSubReg(unsigned R, unsigned SR = 0) : Reg(R), SubReg(SR) {}
explicit RegisterSubReg(const MachineOperand &MO)
@@ -216,16 +217,16 @@ namespace {
void clear() { Map.clear(); }
- bool has(unsigned R) const {
+ bool has(Register R) const {
// All non-virtual registers are considered "bottom".
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
return true;
MapType::const_iterator F = Map.find(R);
return F != Map.end();
}
- const LatticeCell &get(unsigned R) const {
- if (!Register::isVirtualRegister(R))
+ const LatticeCell &get(Register R) const {
+ if (!R.isVirtual())
return Bottom;
MapType::const_iterator F = Map.find(R);
if (F != Map.end())
@@ -234,14 +235,12 @@ namespace {
}
// Invalidates any const references.
- void update(unsigned R, const LatticeCell &L) {
- Map[R] = L;
- }
+ void update(Register R, const LatticeCell &L) { Map[R] = L; }
void print(raw_ostream &os, const TargetRegisterInfo &TRI) const;
private:
- using MapType = std::map<unsigned, LatticeCell>;
+ using MapType = std::map<Register, LatticeCell>;
MapType Map;
// To avoid creating "top" entries, return a const reference to
@@ -633,7 +632,7 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
const MachineOperand &MD = PN.getOperand(0);
RegisterSubReg DefR(MD);
- assert(Register::isVirtualRegister(DefR.Reg));
+ assert(DefR.Reg.isVirtual());
bool Changed = false;
@@ -662,7 +661,7 @@ void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
RegisterSubReg UseR(SO);
// If the input is not a virtual register, we don't really know what
// value it holds.
- if (!Register::isVirtualRegister(UseR.Reg))
+ if (!UseR.Reg.isVirtual())
goto Bottomize;
// If there is no cell for an input register, it means top.
if (!Cells.has(UseR.Reg))
@@ -704,7 +703,7 @@ void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
continue;
RegisterSubReg DefR(MO);
// Only track virtual registers.
- if (!Register::isVirtualRegister(DefR.Reg))
+ if (!DefR.Reg.isVirtual())
continue;
bool Changed = false;
// If the evaluation failed, set cells for all output registers to bottom.
@@ -1086,7 +1085,7 @@ bool MachineConstPropagator::run(MachineFunction &MF) {
bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs,
LatticeCell &RC) {
- if (!Register::isVirtualRegister(R.Reg))
+ if (!R.Reg.isVirtual())
return false;
const LatticeCell &L = Inputs.get(R.Reg);
if (!R.SubReg) {
@@ -1884,7 +1883,7 @@ namespace {
bool evaluateHexVector2(const MachineInstr &MI, const CellMap &Inputs,
CellMap &Outputs);
- void replaceAllRegUsesWith(unsigned FromReg, unsigned ToReg);
+ void replaceAllRegUsesWith(Register FromReg, Register ToReg);
bool rewriteHexBranch(MachineInstr &BrI, const CellMap &Inputs);
bool rewriteHexConstDefs(MachineInstr &MI, const CellMap &Inputs,
bool &AllDefs);
@@ -1942,7 +1941,7 @@ bool HexagonConstEvaluator::evaluate(const MachineInstr &MI,
unsigned Opc = MI.getOpcode();
RegisterSubReg DefR(MD);
assert(!DefR.SubReg);
- if (!Register::isVirtualRegister(DefR.Reg))
+ if (!DefR.Reg.isVirtual())
return false;
if (MI.isCopy()) {
@@ -2809,7 +2808,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
continue;
RegisterSubReg R(MO);
- if (!Register::isVirtualRegister(R.Reg))
+ if (!R.Reg.isVirtual())
continue;
HasUse = true;
// PHIs can legitimately have "top" cells after propagation.
@@ -2851,7 +2850,7 @@ bool HexagonConstEvaluator::rewriteHexConstDefs(MachineInstr &MI,
if (!MO.isReg() || !MO.isDef())
continue;
Register R = MO.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
assert(!MO.getSubReg());
assert(Inputs.has(R));
@@ -3130,10 +3129,10 @@ bool HexagonConstEvaluator::rewriteHexConstUses(MachineInstr &MI,
return Changed;
}
-void HexagonConstEvaluator::replaceAllRegUsesWith(unsigned FromReg,
- unsigned ToReg) {
- assert(Register::isVirtualRegister(FromReg));
- assert(Register::isVirtualRegister(ToReg));
+void HexagonConstEvaluator::replaceAllRegUsesWith(Register FromReg,
+ Register ToReg) {
+ assert(FromReg.isVirtual());
+ assert(ToReg.isVirtual());
for (auto I = MRI->use_begin(FromReg), E = MRI->use_end(); I != E;) {
MachineOperand &O = *I;
++I;
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index a431af17e6d0..d36ffc3da641 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -386,7 +386,7 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B)
if (!MO.isReg() || !MO.isDef())
continue;
Register R = MO.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
if (!isPredicate(R))
continue;
@@ -403,7 +403,7 @@ bool HexagonEarlyIfConversion::usesUndefVReg(const MachineInstr *MI) const {
if (!MO.isReg() || !MO.isUse())
continue;
Register R = MO.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
const MachineInstr *DefI = MRI->getVRegDef(R);
// "Undefined" virtual registers are actually defined via IMPLICIT_DEF.
@@ -493,7 +493,7 @@ unsigned HexagonEarlyIfConversion::countPredicateDefs(
if (!MO.isReg() || !MO.isDef())
continue;
Register R = MO.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
if (isPredicate(R))
PredDefs++;
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index c1d0599830cc..a5cf7397d5a2 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -174,6 +174,7 @@ namespace {
unsigned CoaCounter = 0;
unsigned TfrCounter = 0;
+ // FIXME: Consolidate duplicate definitions of RegisterRef
struct RegisterRef {
RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
Sub(Op.getSubReg()) {}
@@ -187,7 +188,8 @@ namespace {
return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub);
}
- unsigned Reg, Sub;
+ Register Reg;
+ unsigned Sub;
};
using ReferenceMap = DenseMap<unsigned, unsigned>;
@@ -196,25 +198,25 @@ namespace {
unsigned getMaskForSub(unsigned Sub);
bool isCondset(const MachineInstr &MI);
- LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
+ LaneBitmask getLaneMask(Register Reg, unsigned Sub);
void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
- void updateDeadsInRange(unsigned Reg, LaneBitmask LM, LiveRange &Range);
- void updateKillFlags(unsigned Reg);
- void updateDeadFlags(unsigned Reg);
- void recalculateLiveInterval(unsigned Reg);
+ void updateDeadsInRange(Register Reg, LaneBitmask LM, LiveRange &Range);
+ void updateKillFlags(Register Reg);
+ void updateDeadFlags(Register Reg);
+ void recalculateLiveInterval(Register Reg);
void removeInstr(MachineInstr &MI);
- void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
- bool UpdateKills, bool UpdateDeads);
+ void updateLiveness(std::set<Register> &RegSet, bool Recalc,
+ bool UpdateKills, bool UpdateDeads);
unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
MachineBasicBlock::iterator At, unsigned DstR,
unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
bool ReadUndef, bool ImpUse);
- bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs);
+ bool split(MachineInstr &MI, std::set<Register> &UpdRegs);
bool isPredicable(MachineInstr *MI);
MachineInstr *getReachingDefForPred(RegisterRef RD,
@@ -224,19 +226,18 @@ namespace {
void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
MachineBasicBlock::iterator Where,
const MachineOperand &PredOp, bool Cond,
- std::set<unsigned> &UpdRegs);
+ std::set<Register> &UpdRegs);
void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
bool Cond, MachineBasicBlock::iterator First,
MachineBasicBlock::iterator Last);
- bool predicate(MachineInstr &TfrI, bool Cond, std::set<unsigned> &UpdRegs);
- bool predicateInBlock(MachineBasicBlock &B,
- std::set<unsigned> &UpdRegs);
+ bool predicate(MachineInstr &TfrI, bool Cond, std::set<Register> &UpdRegs);
+ bool predicateInBlock(MachineBasicBlock &B, std::set<Register> &UpdRegs);
bool isIntReg(RegisterRef RR, unsigned &BW);
bool isIntraBlocks(LiveInterval &LI);
bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
- bool coalesceSegments(const SmallVectorImpl<MachineInstr*> &Condsets,
- std::set<unsigned> &UpdRegs);
+ bool coalesceSegments(const SmallVectorImpl<MachineInstr *> &Condsets,
+ std::set<Register> &UpdRegs);
};
} // end anonymous namespace
@@ -285,8 +286,8 @@ bool HexagonExpandCondsets::isCondset(const MachineInstr &MI) {
return false;
}
-LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
- assert(Register::isVirtualRegister(Reg));
+LaneBitmask HexagonExpandCondsets::getLaneMask(Register Reg, unsigned Sub) {
+ assert(Reg.isVirtual());
return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
: MRI->getMaxLaneMaskForVReg(Reg);
}
@@ -312,7 +313,7 @@ bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
return false;
}
-void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
+void HexagonExpandCondsets::updateKillFlags(Register Reg) {
auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void {
// Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
MachineInstr *MI = LIS->getInstructionFromIndex(K);
@@ -363,9 +364,9 @@ void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
}
}
-void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
- LiveRange &Range) {
- assert(Register::isVirtualRegister(Reg));
+void HexagonExpandCondsets::updateDeadsInRange(Register Reg, LaneBitmask LM,
+ LiveRange &Range) {
+ assert(Reg.isVirtual());
if (Range.empty())
return;
@@ -374,7 +375,7 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
if (!Op.isReg() || !Op.isDef())
return { false, false };
Register DR = Op.getReg(), DSR = Op.getSubReg();
- if (!Register::isVirtualRegister(DR) || DR != Reg)
+ if (!DR.isVirtual() || DR != Reg)
return { false, false };
LaneBitmask SLM = getLaneMask(DR, DSR);
LaneBitmask A = SLM & LM;
@@ -524,7 +525,7 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
}
}
-void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
+void HexagonExpandCondsets::updateDeadFlags(Register Reg) {
LiveInterval &LI = LIS->getInterval(Reg);
if (LI.hasSubRanges()) {
for (LiveInterval::SubRange &S : LI.subranges()) {
@@ -538,7 +539,7 @@ void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
}
}
-void HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) {
+void HexagonExpandCondsets::recalculateLiveInterval(Register Reg) {
LIS->removeInterval(Reg);
LIS->createAndComputeVirtRegInterval(Reg);
}
@@ -548,12 +549,13 @@ void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
MI.eraseFromParent();
}
-void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
- bool Recalc, bool UpdateKills, bool UpdateDeads) {
+void HexagonExpandCondsets::updateLiveness(std::set<Register> &RegSet,
+ bool Recalc, bool UpdateKills,
+ bool UpdateDeads) {
UpdateKills |= UpdateDeads;
- for (unsigned R : RegSet) {
- if (!Register::isVirtualRegister(R)) {
- assert(Register::isPhysicalRegister(R));
+ for (Register R : RegSet) {
+ if (!R.isVirtual()) {
+ assert(R.isPhysical());
// There shouldn't be any physical registers as operands, except
// possibly reserved registers.
assert(MRI->isReserved(R));
@@ -582,7 +584,7 @@ unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
if (SO.isReg()) {
Register PhysR;
RegisterRef RS = SO;
- if (Register::isVirtualRegister(RS.Reg)) {
+ if (RS.Reg.isVirtual()) {
const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
assert(VC->begin() != VC->end() && "Empty register class");
PhysR = *VC->begin();
@@ -661,7 +663,7 @@ MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
/// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
/// performs all necessary changes to complete the replacement.
bool HexagonExpandCondsets::split(MachineInstr &MI,
- std::set<unsigned> &UpdRegs) {
+ std::set<Register> &UpdRegs) {
if (TfrLimitActive) {
if (TfrCounter >= TfrLimit)
return false;
@@ -803,7 +805,7 @@ bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs,
// For physical register we would need to check register aliases, etc.
// and we don't want to bother with that. It would be of little value
// before the actual register rewriting (from virtual to physical).
- if (!Register::isVirtualRegister(RR.Reg))
+ if (!RR.Reg.isVirtual())
return false;
// No redefs for any operand.
if (isRefInMap(RR, Defs, Exec_Then))
@@ -855,7 +857,7 @@ void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
MachineInstr &MI,
MachineBasicBlock::iterator Where,
const MachineOperand &PredOp, bool Cond,
- std::set<unsigned> &UpdRegs) {
+ std::set<Register> &UpdRegs) {
// The problem with updating live intervals is that we can move one def
// past another def. In particular, this can happen when moving an A2_tfrt
// over an A2_tfrf defining the same register. From the point of view of
@@ -933,7 +935,7 @@ void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
/// the copy under the given condition (using the same predicate register as
/// the copy).
bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
- std::set<unsigned> &UpdRegs) {
+ std::set<Register> &UpdRegs) {
// TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
unsigned Opc = TfrI.getOpcode();
(void)Opc;
@@ -1000,7 +1002,7 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
// subregisters are other physical registers, and we are not checking
// that.
RegisterRef RR = Op;
- if (!Register::isVirtualRegister(RR.Reg))
+ if (!RR.Reg.isVirtual())
return false;
ReferenceMap &Map = Op.isDef() ? Defs : Uses;
@@ -1067,7 +1069,7 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
/// Predicate all cases of conditional copies in the specified block.
bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
- std::set<unsigned> &UpdRegs) {
+ std::set<Register> &UpdRegs) {
bool Changed = false;
MachineBasicBlock::iterator I, E, NextI;
for (I = B.begin(), E = B.end(); I != E; I = NextI) {
@@ -1092,7 +1094,7 @@ bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
}
bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
- if (!Register::isVirtualRegister(RR.Reg))
+ if (!RR.Reg.isVirtual())
return false;
const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
if (RC == &Hexagon::IntRegsRegClass) {
@@ -1187,8 +1189,8 @@ bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
/// the destination register. This could lead to having only one predicated
/// instruction in the end instead of two.
bool HexagonExpandCondsets::coalesceSegments(
- const SmallVectorImpl<MachineInstr*> &Condsets,
- std::set<unsigned> &UpdRegs) {
+ const SmallVectorImpl<MachineInstr *> &Condsets,
+ std::set<Register> &UpdRegs) {
SmallVector<MachineInstr*,16> TwoRegs;
for (MachineInstr *MI : Condsets) {
MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
@@ -1262,7 +1264,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
MF.getFunction().getParent()));
bool Changed = false;
- std::set<unsigned> CoalUpd, PredUpd;
+ std::set<Register> CoalUpd, PredUpd;
SmallVector<MachineInstr*,16> Condsets;
for (auto &B : MF)
@@ -1279,7 +1281,7 @@ bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
// in the IR (they have been removed by live range analysis).
// Updating them right before we split is the easiest, because splitting
// adds definitions which would interfere with updating kills afterwards.
- std::set<unsigned> KillUpd;
+ std::set<Register> KillUpd;
for (MachineInstr *MI : Condsets)
for (MachineOperand &Op : MI->operands())
if (Op.isReg() && Op.isUse())
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index f13dbdf3bb90..a62610ae2b7c 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -306,7 +306,7 @@ static bool needsStackFrame(const MachineBasicBlock &MBB, const BitVector &CSR,
Register R = MO.getReg();
// Virtual registers will need scavenging, which then may require
// a stack slot.
- if (Register::isVirtualRegister(R))
+ if (R.isVirtual())
return true;
for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
if (CSR[*S])
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index 2f29e88bc989..f27dd9f4fc36 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -613,7 +613,7 @@ void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const {
if (MO.isReg() && MO.isDef()) {
Register R = MO.getReg();
assert(MO.getSubReg() == 0 && "Unexpected subregister in definition");
- if (Register::isVirtualRegister(R))
+ if (R.isVirtual())
RO.insert(std::make_pair(R, Index++));
}
}
@@ -730,7 +730,7 @@ void HexagonGenInsert::getInstrDefs(const MachineInstr *MI,
if (!MO.isReg() || !MO.isDef())
continue;
Register R = MO.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
Defs.insert(R);
}
@@ -743,7 +743,7 @@ void HexagonGenInsert::getInstrUses(const MachineInstr *MI,
if (!MO.isReg() || !MO.isUse())
continue;
Register R = MO.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
Uses.insert(R);
}
@@ -1483,7 +1483,7 @@ bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) {
if (!MO.isReg() || !MO.isDef())
continue;
Register R = MO.getReg();
- if (!Register::isVirtualRegister(R) || !MRI->use_nodbg_empty(R)) {
+ if (!R.isVirtual() || !MRI->use_nodbg_empty(R)) {
AllDead = false;
break;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index 903287e68c99..d8d2025c5d27 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -48,7 +48,8 @@ namespace {
// FIXME: Use TargetInstrInfo::RegSubRegPair
struct RegisterSubReg {
- unsigned R, S;
+ Register R;
+ unsigned S;
RegisterSubReg(unsigned r = 0, unsigned s = 0) : R(r), S(s) {}
RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
@@ -111,7 +112,7 @@ namespace {
VectOfInst PUsers;
RegToRegMap G2P;
- bool isPredReg(unsigned R);
+ bool isPredReg(Register R);
void collectPredicateGPR(MachineFunction &MF);
void processPredicateGPR(const RegisterSubReg &Reg);
unsigned getPredForm(unsigned Opc);
@@ -133,8 +134,8 @@ INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
INITIALIZE_PASS_END(HexagonGenPredicate, "hexagon-gen-pred",
"Hexagon generate predicate operations", false, false)
-bool HexagonGenPredicate::isPredReg(unsigned R) {
- if (!Register::isVirtualRegister(R))
+bool HexagonGenPredicate::isPredReg(Register R) {
+ if (!R.isVirtual())
return false;
const TargetRegisterClass *RC = MRI->getRegClass(R);
return RC == &Hexagon::PredRegsRegClass;
@@ -214,7 +215,7 @@ void HexagonGenPredicate::collectPredicateGPR(MachineFunction &MF) {
case TargetOpcode::COPY:
if (isPredReg(MI->getOperand(1).getReg())) {
RegisterSubReg RD = MI->getOperand(0);
- if (Register::isVirtualRegister(RD.R))
+ if (RD.R.isVirtual())
PredGPRs.insert(RD);
}
break;
@@ -246,7 +247,7 @@ RegisterSubReg HexagonGenPredicate::getPredRegFor(const RegisterSubReg &Reg) {
// Create a predicate register for a given Reg. The newly created register
// will have its value copied from Reg, so that it can be later used as
// an operand in other instructions.
- assert(Register::isVirtualRegister(Reg.R));
+ assert(Reg.R.isVirtual());
RegToRegMap::iterator F = G2P.find(Reg);
if (F != G2P.end())
return F->second;
@@ -472,9 +473,9 @@ bool HexagonGenPredicate::eliminatePredCopies(MachineFunction &MF) {
continue;
RegisterSubReg DR = MI.getOperand(0);
RegisterSubReg SR = MI.getOperand(1);
- if (!Register::isVirtualRegister(DR.R))
+ if (!DR.R.isVirtual())
continue;
- if (!Register::isVirtualRegister(SR.R))
+ if (!SR.R.isVirtual())
continue;
if (MRI->getRegClass(DR.R) != PredRC)
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 43e0958fc3ab..2f23e8643720 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1432,7 +1432,7 @@ bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow(
Register Reg = InitVal->getReg();
// We don't know the value of a physical register.
- if (!Register::isVirtualRegister(Reg))
+ if (!Reg.isVirtual())
return true;
MachineInstr *Def = MRI->getVRegDef(Reg);
@@ -1510,7 +1510,7 @@ bool HexagonHardwareLoops::checkForImmediate(const MachineOperand &MO,
int64_t TV;
Register R = MO.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
return false;
MachineInstr *DI = MRI->getVRegDef(R);
unsigned DOpc = DI->getOpcode();
diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
index d0b02f035d1e..fc31139e13ce 100644
--- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
@@ -139,8 +139,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
Register DstReg = Dst.getReg();
Register SrcReg = Src.getReg();
// Just handle virtual registers.
- if (Register::isVirtualRegister(DstReg) &&
- Register::isVirtualRegister(SrcReg)) {
+ if (DstReg.isVirtual() && SrcReg.isVirtual()) {
// Map the following:
// %170 = SXTW %166
// PeepholeMap[170] = %166
@@ -188,8 +187,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
Register DstReg = Dst.getReg();
Register SrcReg = Src.getReg();
// Just handle virtual registers.
- if (Register::isVirtualRegister(DstReg) &&
- Register::isVirtualRegister(SrcReg)) {
+ if (DstReg.isVirtual() && SrcReg.isVirtual()) {
// Map the following:
// %170 = NOT_xx %166
// PeepholeMap[170] = %166
@@ -210,8 +208,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
Register DstReg = Dst.getReg();
Register SrcReg = Src.getReg();
- if (Register::isVirtualRegister(DstReg) &&
- Register::isVirtualRegister(SrcReg)) {
+ if (DstReg.isVirtual() && SrcReg.isVirtual()) {
// Try to find in the map.
if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
// Change the 1st operand.
@@ -242,7 +239,7 @@ bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
if (RC0->getID() == Hexagon::PredRegsRegClassID) {
// Handle instructions that have a prediate register in op0
// (most cases of predicable instructions).
- if (Register::isVirtualRegister(Reg0)) {
+ if (Reg0.isVirtual()) {
// Try to find in the map.
if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
// Change the 1st operand and, flip the opcode.
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index b45d871e04d6..60c2feb766cc 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -97,7 +97,7 @@ namespace {
bool isFixedInstr(const MachineInstr *MI) const;
void partitionRegisters(UUSetMap &P2Rs);
int32_t profit(const MachineInstr *MI) const;
- int32_t profit(unsigned Reg) const;
+ int32_t profit(Register Reg) const;
bool isProfitable(const USet &Part, LoopRegMap &IRM) const;
void collectIndRegsForLoop(const MachineLoop *L, USet &Rs);
@@ -211,7 +211,7 @@ bool HexagonSplitDoubleRegs::isFixedInstr(const MachineInstr *MI) const {
if (!Op.isReg())
continue;
Register R = Op.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
return true;
}
return false;
@@ -259,7 +259,7 @@ void HexagonSplitDoubleRegs::partitionRegisters(UUSetMap &P2Rs) {
if (&MO == &Op || !MO.isReg() || MO.getSubReg())
continue;
Register T = MO.getReg();
- if (!Register::isVirtualRegister(T)) {
+ if (!T.isVirtual()) {
FixedRegs.set(x);
continue;
}
@@ -399,8 +399,8 @@ int32_t HexagonSplitDoubleRegs::profit(const MachineInstr *MI) const {
return 0;
}
-int32_t HexagonSplitDoubleRegs::profit(unsigned Reg) const {
- assert(Register::isVirtualRegister(Reg));
+int32_t HexagonSplitDoubleRegs::profit(Register Reg) const {
+ assert(Reg.isVirtual());
const MachineInstr *DefI = MRI->getVRegDef(Reg);
switch (DefI->getOpcode()) {
@@ -605,7 +605,7 @@ void HexagonSplitDoubleRegs::createHalfInstr(unsigned Opc, MachineInstr *MI,
// For register operands, set the subregister.
Register R = Op.getReg();
unsigned SR = Op.getSubReg();
- bool isVirtReg = Register::isVirtualRegister(R);
+ bool isVirtReg = R.isVirtual();
bool isKill = Op.isKill();
if (isVirtReg && MRI->getRegClass(R) == DoubleRC) {
isKill = false;
@@ -1106,7 +1106,7 @@ void HexagonSplitDoubleRegs::collapseRegPairs(MachineInstr *MI,
if (!Op.isReg() || !Op.isUse())
continue;
Register R = Op.getReg();
- if (!Register::isVirtualRegister(R))
+ if (!R.isVirtual())
continue;
if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index fe1582a59c7a..76fe0bec92e3 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -474,14 +474,14 @@ void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
for (auto &I : Src->Succs) {
if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
continue;
- unsigned DepR = I.getReg();
+ Register DepR = I.getReg();
int DefIdx = -1;
for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
const MachineOperand &MO = SrcI->getOperand(OpNum);
bool IsSameOrSubReg = false;
if (MO.isReg()) {
- unsigned MOReg = MO.getReg();
- if (Register::isVirtualRegister(DepR)) {
+ Register MOReg = MO.getReg();
+ if (DepR.isVirtual()) {
IsSameOrSubReg = (MOReg == DepR);
} else {
IsSameOrSubReg = getRegisterInfo()->isSubRegisterEq(DepR, MOReg);
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