[PATCH] D91705: Fix unused variables in release build

[Mikhail Goncharov via Phabricator via llvm-commits]

goncharov created this revision.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.
goncharov requested review of this revision.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91705

Files:
  llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp


Index: llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -1569,7 +1569,7 @@
       auto Next = ++MachineBasicBlock::iterator(VPST);
       assert(getVPTInstrPredicate(*Next) != ARMVCC::None &&
              "The instruction after a VPST must be predicated");
-
+      (void)Next;
       MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR);
       if (VprDef && VCMPOpcodeToVPT(VprDef->getOpcode()) &&
           !LoLoop.ToRemove.contains(VprDef)) {
@@ -1578,13 +1578,11 @@
         // the same values at the VPST
         if (RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(1).getReg()) &&
             RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(2).getReg())) {
-          bool IntermediateInstrsUseVPR =
-              std::any_of(++MachineBasicBlock::iterator(VCMP),
-                          MachineBasicBlock::iterator(VPST), hasVPRUse);
           // If the instruction after the VCMP is predicated then a different
           // code path is expected to have merged the VCMP and VPST already.
           // This assertion protects against changes to that behaviour
-          assert(!IntermediateInstrsUseVPR &&
+          assert(!std::any_of(++MachineBasicBlock::iterator(VCMP),
+                              MachineBasicBlock::iterator(VPST), hasVPRUse) &&
                  "Instructions between the VCMP and VPST are not expected to "
                  "be predicated");
           ReplaceVCMPWithVPT(VCMP, VPST);


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