[llvm] da2e472 - [ARM][LowOverheadLoops] Merge VCMP and VPST across VPT blocks
Sam Tebbs via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 18 04:54:43 PST 2020
Author: Sam Tebbs
Date: 2020-11-18T12:54:16Z
New Revision: da2e4728c71f9f8569246fb881c21811f8182c75
URL: https://github.com/llvm/llvm-project/commit/da2e4728c71f9f8569246fb881c21811f8182c75
DIFF: https://github.com/llvm/llvm-project/commit/da2e4728c71f9f8569246fb881c21811f8182c75.diff
LOG: [ARM][LowOverheadLoops] Merge VCMP and VPST across VPT blocks
This patch adds support for combining a VPST with a dangling VCMP from a
previous VPT block.
Differential Revision: https://reviews.llvm.org/D90935
Added:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir
Modified:
llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
index bde17cc055b5..6ed6260c05e4 100644
--- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
+++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp
@@ -87,8 +87,8 @@ static bool isVectorPredicate(MachineInstr *MI) {
return MI->findRegisterDefOperandIdx(ARM::VPR) != -1;
}
-static bool hasVPRUse(MachineInstr *MI) {
- return MI->findRegisterUseOperandIdx(ARM::VPR) != -1;
+static bool hasVPRUse(MachineInstr &MI) {
+ return MI.findRegisterUseOperandIdx(ARM::VPR) != -1;
}
static bool isDomainMVE(MachineInstr *MI) {
@@ -97,8 +97,7 @@ static bool isDomainMVE(MachineInstr *MI) {
}
static bool shouldInspect(MachineInstr &MI) {
- return isDomainMVE(&MI) || isVectorPredicate(&MI) ||
- hasVPRUse(&MI);
+ return isDomainMVE(&MI) || isVectorPredicate(&MI) || hasVPRUse(MI);
}
static bool isDo(MachineInstr *MI) {
@@ -1485,14 +1484,33 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
for (auto &Block : LoLoop.getVPTBlocks()) {
SmallVectorImpl<MachineInstr *> &Insts = Block.getInsts();
- if (VPTState::isEntryPredicatedOnVCTP(Block, /*exclusive*/true)) {
+ auto ReplaceVCMPWithVPT = [&](MachineInstr *&TheVCMP, MachineInstr *At) {
+ assert(TheVCMP && "Replacing a removed or non-existent VCMP");
+ // Replace the VCMP with a VPT
+ MachineInstrBuilder MIB =
+ BuildMI(*At->getParent(), At, At->getDebugLoc(),
+ TII->get(VCMPOpcodeToVPT(TheVCMP->getOpcode())));
+ MIB.addImm(ARMVCC::Then);
+ // Register one
+ MIB.add(TheVCMP->getOperand(1));
+ // Register two
+ MIB.add(TheVCMP->getOperand(2));
+ // The comparison code, e.g. ge, eq, lt
+ MIB.add(TheVCMP->getOperand(3));
+ LLVM_DEBUG(dbgs() << "ARM Loops: Combining with VCMP to VPT: " << *MIB);
+ LoLoop.BlockMasksToRecompute.insert(MIB.getInstr());
+ LoLoop.ToRemove.insert(TheVCMP);
+ TheVCMP = nullptr;
+ };
+
+ if (VPTState::isEntryPredicatedOnVCTP(Block, /*exclusive*/ true)) {
+ MachineInstr *VPST = Insts.front();
if (VPTState::hasUniformPredicate(Block)) {
// A vpt block starting with VPST, is only predicated upon vctp and has no
// internal vpr defs:
// - Remove vpst.
// - Unpredicate the remaining instructions.
- LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *Insts.front());
- LoLoop.ToRemove.insert(Insts.front());
+ LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
for (unsigned i = 1; i < Insts.size(); ++i)
RemovePredicate(Insts[i]);
} else {
@@ -1503,10 +1521,7 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
// we come across the divergent vpr def.
// - Insert a new vpst to predicate the instruction(s) that following
// the divergent vpr def.
- // TODO: We could be producing more VPT blocks than necessary and could
- // fold the newly created one into a proceeding one.
MachineInstr *Divergent = VPTState::getDivergent(Block);
- MachineInstr *VPST = Insts.front();
auto DivergentNext = ++MachineBasicBlock::iterator(Divergent);
bool DivergentNextIsPredicated =
getVPTInstrPredicate(*DivergentNext) != ARMVCC::None;
@@ -1520,24 +1535,6 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
MachineInstr *VCMP =
VCMPOpcodeToVPT(Divergent->getOpcode()) != 0 ? Divergent : nullptr;
- auto ReplaceVCMPWithVPT = [&]() {
- // Replace the VCMP with a VPT
- MachineInstrBuilder MIB = BuildMI(
- *Divergent->getParent(), Divergent, Divergent->getDebugLoc(),
- TII->get(VCMPOpcodeToVPT(VCMP->getOpcode())));
- MIB.addImm(ARMVCC::Then);
- // Register one
- MIB.add(VCMP->getOperand(1));
- // Register two
- MIB.add(VCMP->getOperand(2));
- // The comparison code, e.g. ge, eq, lt
- MIB.add(VCMP->getOperand(3));
- LLVM_DEBUG(dbgs()
- << "ARM Loops: Combining with VCMP to VPT: " << *MIB);
- LoLoop.BlockMasksToRecompute.insert(MIB.getInstr());
- LoLoop.ToRemove.insert(VCMP);
- };
-
if (DivergentNextIsPredicated) {
// Insert a VPST at the divergent only if the next instruction
// would actually use it. A VCMP following a VPST can be
@@ -1553,17 +1550,48 @@ void ARMLowOverheadLoops::ConvertVPTBlocks(LowOverheadLoop &LoLoop) {
LoLoop.BlockMasksToRecompute.insert(MIB.getInstr());
} else {
// No RDA checks are necessary here since the VPST would have been
- // directly before the VCMP
- ReplaceVCMPWithVPT();
+ // directly after the VCMP
+ ReplaceVCMPWithVPT(VCMP, VCMP);
}
}
- LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
- LoLoop.ToRemove.insert(VPST);
}
+ LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
+ LoLoop.ToRemove.insert(VPST);
} else if (Block.containsVCTP()) {
// The vctp will be removed, so the block mask of the vp(s)t will need
// to be recomputed.
LoLoop.BlockMasksToRecompute.insert(Insts.front());
+ } else if (Insts.front()->getOpcode() == ARM::MVE_VPST) {
+ // If this block starts with a VPST then attempt to merge it with the
+ // preceeding un-merged VCMP into a VPT. This VCMP comes from a VPT
+ // block that no longer exists
+ MachineInstr *VPST = Insts.front();
+ auto Next = ++MachineBasicBlock::iterator(VPST);
+ assert(getVPTInstrPredicate(*Next) != ARMVCC::None &&
+ "The instruction after a VPST must be predicated");
+
+ MachineInstr *VprDef = RDA->getUniqueReachingMIDef(VPST, ARM::VPR);
+ if (VprDef && VCMPOpcodeToVPT(VprDef->getOpcode()) &&
+ !LoLoop.ToRemove.contains(VprDef)) {
+ MachineInstr *VCMP = VprDef;
+ // The VCMP and VPST can only be merged if the VCMP's operands will have
+ // the same values at the VPST
+ if (RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(1).getReg()) &&
+ RDA->hasSameReachingDef(VCMP, VPST, VCMP->getOperand(2).getReg())) {
+ bool IntermediateInstrsUseVPR =
+ std::any_of(++MachineBasicBlock::iterator(VCMP),
+ MachineBasicBlock::iterator(VPST), hasVPRUse);
+ // If the instruction after the VCMP is predicated then a
diff erent
+ // code path is expected to have merged the VCMP and VPST already.
+ // This assertion protects against changes to that behaviour
+ assert(!IntermediateInstrsUseVPR &&
+ "Instructions between the VCMP and VPST are not expected to "
+ "be predicated");
+ ReplaceVCMPWithVPT(VCMP, VPST);
+ LLVM_DEBUG(dbgs() << "ARM Loops: Removing VPST: " << *VPST);
+ LoLoop.ToRemove.insert(VPST);
+ }
+ }
}
}
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir
new file mode 100644
index 000000000000..0ed94da7d2a4
--- /dev/null
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination-across-blocks.mir
@@ -0,0 +1,479 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
+
+--- |
+ define void @combine_previous() {
+ while.end6:
+ ret void
+ }
+
+ define void @combine_middle() {
+ while.end6:
+ ret void
+ }
+
+ define void @combine_last() {
+ while.end6:
+ ret void
+ }
+
+ define void @no_combination_
diff _reg_value() {
+ while.end6:
+ ret void
+ }
+
+ define void @no_combination_vcmp_already_merged() {
+ while.end6:
+ ret void
+ }
+
+...
+---
+name: combine_previous
+alignment: 8
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+debugValueSubstitutions: []
+constants:
+ - id: 0
+ value: float 0xC7EFFFFFE0000000
+ alignment: 4
+ isTargetSpecific: false
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: combine_previous
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
+ ; CHECK: bb.1 (align 4):
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
+ ; CHECK: renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q0
+ ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
+ ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK: bb.2:
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+ ; CHECK: bb.3 (align 4):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
+ bb.0:
+ successors: %bb.6(0x80000000)
+ liveins: $r0, $r1, $r2
+
+ renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
+ renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
+ $lr = t2DoLoopStart renamable $lr
+
+ bb.6 (align 4):
+ successors: %bb.6(0x7c000000), %bb.8(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2
+
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
+ renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
+ MVE_VPST 8, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
+ MVE_VPST 4, implicit $vpr
+ renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, renamable $q0
+ renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
+ MVE_VPST 8, implicit $vpr
+ renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q0
+ t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
+ tB %bb.8, 14 /* CC::al */, $noreg
+
+ bb.8:
+ liveins: $r2, $r12, $q0
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+ bb.9 (align 4):
+ CONSTPOOL_ENTRY 0, %const.0, 4
+
+...
+---
+name: combine_middle
+alignment: 8
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+debugValueSubstitutions: []
+constants:
+ - id: 0
+ value: float 0xC7EFFFFFE0000000
+ alignment: 4
+ isTargetSpecific: false
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: combine_middle
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $q2, $r0, $r1
+ ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
+ ; CHECK: bb.1 (align 4):
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $q2, $r0
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
+ ; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q2
+ ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
+ ; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
+ ; CHECK: MVE_VPST 4, implicit $vpr
+ ; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK: bb.2:
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+ ; CHECK: bb.3 (align 4):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
+ bb.0:
+ successors: %bb.6(0x80000000)
+ liveins: $r0, $r1, $r2
+
+ renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
+ renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
+ $lr = t2DoLoopStart renamable $lr
+
+ bb.6 (align 4):
+ successors: %bb.6(0x7c000000), %bb.8(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2, $q2
+
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
+ renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
+ MVE_VPST 2, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
+ renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
+ renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
+ MVE_VPST 8, implicit $vpr
+ renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
+ MVE_VPST 4, implicit $vpr
+ renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
+ t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
+ tB %bb.8, 14 /* CC::al */, $noreg
+
+ bb.8:
+ liveins: $r2, $r12, $q0
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+ bb.9 (align 4):
+ CONSTPOOL_ENTRY 0, %const.0, 4
+
+...
+---
+name: combine_last
+alignment: 8
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+debugValueSubstitutions: []
+constants:
+ - id: 0
+ value: float 0xC7EFFFFFE0000000
+ alignment: 4
+ isTargetSpecific: false
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: combine_last
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $q2, $r0, $r1
+ ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
+ ; CHECK: bb.1 (align 4):
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $q2, $r0
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
+ ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
+ ; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q2
+ ; CHECK: MVE_VPTv4f32 8, renamable $q2, renamable $q1, 12, implicit-def $vpr
+ ; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK: bb.2:
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+ ; CHECK: bb.3 (align 4):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
+ bb.0:
+ successors: %bb.6(0x80000000)
+ liveins: $r0, $r1, $r2
+
+ renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
+ renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
+ $lr = t2DoLoopStart renamable $lr
+
+ bb.6 (align 4):
+ successors: %bb.6(0x7c000000), %bb.8(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2, $q2
+
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
+ renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
+ MVE_VPST 8, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
+ MVE_VPST 2, implicit $vpr
+ renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
+ renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
+ renamable $vpr = MVE_VCMPf32 renamable $q2, renamable $q1, 12, 1, killed renamable $vpr
+ MVE_VPST 8, implicit $vpr
+ renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
+ t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
+ tB %bb.8, 14 /* CC::al */, $noreg
+
+ bb.8:
+ liveins: $r2, $r12, $q0
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+ bb.9 (align 4):
+ CONSTPOOL_ENTRY 0, %const.0, 4
+
+...
+---
+name: no_combination_
diff _reg_value
+alignment: 8
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+debugValueSubstitutions: []
+constants:
+ - id: 0
+ value: float 0xC7EFFFFFE0000000
+ alignment: 4
+ isTargetSpecific: false
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: no_combination_
diff _reg_value
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $r0, $r1
+ ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
+ ; CHECK: bb.1 (align 4):
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $r0
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
+ ; CHECK: renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 0, $noreg, killed renamable $q1
+ ; CHECK: renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 0, killed $noreg
+ ; CHECK: renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q0
+ ; CHECK: MVE_VPST 8, implicit $vpr
+ ; CHECK: renamable $q0 = MVE_VORR killed renamable $q1, killed renamable $q1, 1, killed renamable $vpr, killed renamable $q0
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK: bb.2:
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+ ; CHECK: bb.3 (align 4):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
+ bb.0:
+ successors: %bb.6(0x80000000)
+ liveins: $r0, $r1, $r2
+
+ renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
+ renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
+ $lr = t2DoLoopStart renamable $lr
+
+ bb.6 (align 4):
+ successors: %bb.6(0x7c000000), %bb.8(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2
+
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
+ renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
+ MVE_VPST 8, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
+ MVE_VPST 4, implicit $vpr
+ renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
+ renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
+ renamable $q0 = MVE_VORR renamable $q1, renamable $q1, 0, $noreg, killed renamable $q0
+ MVE_VPST 8, implicit $vpr
+ renamable $q0 = MVE_VORR killed renamable $q1, renamable $q1, 1, killed renamable $vpr, killed renamable $q0
+ t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
+ tB %bb.8, 14 /* CC::al */, $noreg
+
+ bb.8:
+ liveins: $r2, $r12, $q0
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+ bb.9 (align 4):
+ CONSTPOOL_ENTRY 0, %const.0, 4
+
+...
+---
+name: no_combination_vcmp_already_merged
+alignment: 8
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+hasWinCFI: false
+registers: []
+liveins:
+ - { reg: '$r0', virtual-reg: '' }
+ - { reg: '$r1', virtual-reg: '' }
+ - { reg: '$r2', virtual-reg: '' }
+frameInfo:
+fixedStack: []
+stack:
+ - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
+ stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites: []
+debugValueSubstitutions: []
+constants:
+ - id: 0
+ value: float 0xC7EFFFFFE0000000
+ alignment: 4
+ isTargetSpecific: false
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: no_combination_vcmp_already_merged
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: $q2, $r0, $r1
+ ; CHECK: renamable $q0 = MVE_VDUP32 renamable $r1, 0, $noreg, undef renamable $q0
+ ; CHECK: $lr = MVE_DLSTP_32 killed renamable $r1
+ ; CHECK: bb.1 (align 4):
+ ; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+ ; CHECK: liveins: $lr, $q0, $q2, $r0
+ ; CHECK: renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg
+ ; CHECK: MVE_VPTv4f32 8, renamable $q1, renamable $q0, 12, implicit-def $vpr
+ ; CHECK: renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
+ ; CHECK: MVE_VPST 8, implicit $vpr
+ ; CHECK: dead renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, killed renamable $vpr, killed renamable $q1
+ ; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
+ ; CHECK: bb.2:
+ ; CHECK: frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+ ; CHECK: bb.3 (align 4):
+ ; CHECK: CONSTPOOL_ENTRY 0, %const.0, 4
+ bb.0:
+ successors: %bb.6(0x80000000)
+ liveins: $r0, $r1, $r2
+
+ renamable $r3, dead $cpsr = nuw nsw tADDi3 renamable $r1, 3, 14 /* CC::al */, $noreg
+ renamable $q0 = MVE_VDUP32 killed renamable $r1, 0, $noreg, undef renamable $q0
+ renamable $r3 = t2ANDri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $lr = t2SUBri killed renamable $r3, 4, 14 /* CC::al */, $noreg, $noreg
+ renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
+ renamable $lr = nuw nsw t2ADDrs killed renamable $r3, killed renamable $lr, 19, 14 /* CC::al */, $noreg, $noreg
+ $lr = t2DoLoopStart renamable $lr
+
+ bb.6 (align 4):
+ successors: %bb.6(0x7c000000), %bb.8(0x04000000)
+ liveins: $lr, $q0, $r0, $r1, $r2, $q2
+
+ renamable $lr = t2LoopDec killed renamable $lr, 1
+ renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg
+ renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
+ MVE_VPST 8, implicit $vpr
+ renamable $r0, renamable $q1 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr
+ MVE_VPST 4, implicit $vpr
+ renamable $vpr = MVE_VCMPf32 renamable $q1, renamable $q0, 12, 1, killed renamable $vpr
+ renamable $q2 = MVE_VORR renamable $q1, renamable $q1, 1, renamable $vpr, killed renamable $q2
+ MVE_VPST 8, implicit $vpr
+ renamable $q1 = MVE_VORR killed renamable $q1, renamable $q0, 1, renamable $vpr, renamable $q1
+ t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
+ tB %bb.8, 14 /* CC::al */, $noreg
+
+ bb.8:
+ liveins: $r2, $r12, $q0
+ frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc
+
+ bb.9 (align 4):
+ CONSTPOOL_ENTRY 0, %const.0, 4
+
+...
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