[PATCH] D89047: [AVR] Optimize 8-bit logic left/right shifts

[Dylan McKay via Phabricator via llvm-commits]

dylanmckay requested changes to this revision.
dylanmckay added a comment.
This revision now requires changes to proceed.

Nice patch, cheers.

Just a small comment around a latent FIXME, then it's good to approve.



================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:353
+      // TODO
+      // } else if (Op.getOpcode() == ISD::SHL && ShiftAmount == 7) {
+      // } else if (Op.getOpcode() == ISD::SRL && ShiftAmount == 7) {
----------------
> Now llvm-avr generates the same asm for 8-bit shifts as AVR-GCC does, when ShiftAmount = 1,2,3,4,5,6, 7.

This suggests that either this `TODO` comment is now unnecessary, or there is another optimization that could be implemented specifically for 7-bit shifts that AVR-GCC does not implement.

Remove the TODO comment, or, if you feel it is important, add a sentence describing the TODO


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D89047/new/

https://reviews.llvm.org/D89047