[PATCH] D91638: [RISCV] Add a proof-of-concept for supporting non-scalable vectors in RVV

[Fraser Cormack via Phabricator via llvm-commits]

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Hidden behind a compilation option `-riscv-non-scalable-vectors`, the
RISC-V backend may now compile simple functions for non-scalable v4i32
and v8i32 vector types. It builds on top of D89449 <https://reviews.llvm.org/D89449>.

The approach is VLEN-agnostic but assumes VLEN>=128, much like the
scalable RVV support (N.B: scalable is currently >= 64 but may be
made >= 128?). This allows the compiler to support any 128-bit vector type
with a consistent ABI:

  v2i8:   e8,  m1, AVL=2
  v4i32:  e32, m1, AVL=4
  v8i32:  e32, m2, AVL=8
  v16i32: e32, m4, AVL=16
  v16i64: e64, m8, AVL=16

There are tradeoffs to this design. Requiring an LMUL=8 for v16i64 even when VLEN>=1024 could fit it in LMUL=1 is an example.

Other designs are available, such as by supporting non-scalable vectors by compiling for a specific VLEN, and/or by using VLMAX equal to the vector length. It's not clear to me how well LLVM would cope with this design, though.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91638

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoPseudoV.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/load-add-store-nonscale.ll

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