[llvm] e67d885 - [AMDGPU] Precommit more vccz workaround tests
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 17 08:01:29 PST 2020
Author: Jay Foad
Date: 2020-11-17T15:55:40Z
New Revision: e67d8859f205308d9e799c8448dcc1dcedc30102
URL: https://github.com/llvm/llvm-project/commit/e67d8859f205308d9e799c8448dcc1dcedc30102
DIFF: https://github.com/llvm/llvm-project/commit/e67d8859f205308d9e799c8448dcc1dcedc30102.diff
LOG: [AMDGPU] Precommit more vccz workaround tests
Added:
Modified:
llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
index c6ef43d93326..79233141070d 100644
--- a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
+++ b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
@@ -163,3 +163,167 @@ body: |
bb.1:
...
+---
+# Test vcc definition in a previous basic block.
+
+# CHECK-LABEL: name: vcc_def_pred
+# CHECK: bb.1:
+# CHECK: S_CBRANCH_VCCZ %bb.2, implicit $vcc
+
+name: vcc_def_pred
+body: |
+ bb.0:
+ $vcc = S_MOV_B64 0
+ bb.1:
+ S_CBRANCH_VCCZ %bb.2, implicit $vcc
+ bb.2:
+
+...
+
+# Test various ways that the live range of vccz can overlap with the live range
+# of an outstanding smem load.
+
+---
+# CHECK-LABEL: name: load_wait_def_use
+# SI: S_WAITCNT 0
+# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+# SI-NEXT: S_WAITCNT 127
+# SI-NEXT: $vcc = S_MOV_B64 0
+# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
+name: load_wait_def_use
+body: |
+ bb.0:
+ $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+ S_WAITCNT 127
+ $vcc = S_MOV_B64 0
+ S_CBRANCH_VCCZ %bb.1, implicit $vcc
+ bb.1:
+...
+
+---
+# CHECK-LABEL: name: load_wait_nop_def_use
+# SI: S_WAITCNT 0
+# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+# SI-NEXT: S_WAITCNT 127
+# SI-NEXT: S_NOP 0
+# SI-NEXT: $vcc = S_MOV_B64 0
+# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
+name: load_wait_nop_def_use
+body: |
+ bb.0:
+ $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+ S_WAITCNT 127
+ S_NOP 0
+ $vcc = S_MOV_B64 0
+ S_CBRANCH_VCCZ %bb.1, implicit $vcc
+ bb.1:
+...
+
+---
+# CHECK-LABEL: name: load_def_wait_use
+# SI: S_WAITCNT 0
+# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+# SI-NEXT: $vcc = S_MOV_B64 0
+# SI-NEXT: S_WAITCNT 127
+# SI-NEXT: $vcc = S_MOV_B64 $vcc
+# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
+name: load_def_wait_use
+body: |
+ bb.0:
+ $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+ $vcc = S_MOV_B64 0
+ S_WAITCNT 127
+ S_CBRANCH_VCCZ %bb.1, implicit $vcc
+ bb.1:
+...
+
+# CHECK-LABEL: name: load_def_wait_nop_use
+# SI: S_WAITCNT 0
+# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+# SI-NEXT: $vcc = S_MOV_B64 0
+# SI-NEXT: S_WAITCNT 127
+# SI-NEXT: S_NOP 0
+# FIXME should have $vcc = S_MOV_B64 $vcc
+# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
+name: load_def_wait_nop_use
+body: |
+ bb.0:
+ $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+ $vcc = S_MOV_B64 0
+ S_WAITCNT 127
+ S_NOP 0
+ S_CBRANCH_VCCZ %bb.1, implicit $vcc
+ bb.1:
+...
+
+---
+# CHECK-LABEL: name: load_def_use
+# SI: S_WAITCNT 0
+# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+# SI-NEXT: $vcc = S_MOV_B64 0
+# SI-NEXT: S_WAITCNT 127
+# SI-NEXT: $vcc = S_MOV_B64 $vcc
+# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
+name: load_def_use
+body: |
+ bb.0:
+ $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+ $vcc = S_MOV_B64 0
+ S_CBRANCH_VCCZ %bb.1, implicit $vcc
+ bb.1:
+...
+
+---
+# CHECK-LABEL: name: def_load_wait_use
+# SI: S_WAITCNT 0
+# SI-NEXT: $vcc = S_MOV_B64 0
+# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+# SI-NEXT: S_WAITCNT 127
+# SI-NEXT: $vcc = S_MOV_B64 $vcc
+# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
+name: def_load_wait_use
+body: |
+ bb.0:
+ $vcc = S_MOV_B64 0
+ $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+ S_WAITCNT 127
+ S_CBRANCH_VCCZ %bb.1, implicit $vcc
+ bb.1:
+...
+
+---
+# CHECK-LABEL: name: def_load_wait_nop_use
+# SI: S_WAITCNT 0
+# SI-NEXT: $vcc = S_MOV_B64 0
+# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+# SI-NEXT: S_WAITCNT 127
+# SI-NEXT: S_NOP 0
+# FIXME should have $vcc = S_MOV_B64 $vcc
+# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
+name: def_load_wait_nop_use
+body: |
+ bb.0:
+ $vcc = S_MOV_B64 0
+ $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+ S_WAITCNT 127
+ S_NOP 0
+ S_CBRANCH_VCCZ %bb.1, implicit $vcc
+ bb.1:
+...
+
+---
+# CHECK-LABEL: name: def_load_use
+# SI: S_WAITCNT 0
+# SI-NEXT: $vcc = S_MOV_B64 0
+# SI-NEXT: $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+# SI-NEXT: S_WAITCNT 127
+# SI-NEXT: $vcc = S_MOV_B64 $vcc
+# SI-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc
+name: def_load_use
+body: |
+ bb.0:
+ $vcc = S_MOV_B64 0
+ $sgpr0 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
+ S_CBRANCH_VCCZ %bb.1, implicit $vcc
+ bb.1:
+...
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