[llvm] 498859c - [TableGen] Clean up Target .td include files
Paul C. Anagnostopoulos via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 17 06:45:48 PST 2020
Author: Paul C. Anagnostopoulos
Date: 2020-11-17T09:45:14-05:00
New Revision: 498859cbf6682d63e9dfdfc89d298481261cf1dd
URL: https://github.com/llvm/llvm-project/commit/498859cbf6682d63e9dfdfc89d298481261cf1dd
DIFF: https://github.com/llvm/llvm-project/commit/498859cbf6682d63e9dfdfc89d298481261cf1dd.diff
LOG: [TableGen] Clean up Target .td include files
Differential Revision: https://reviews.llvm.org/D91483
Added:
Modified:
llvm/include/llvm/Target/GenericOpcodes.td
llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
llvm/include/llvm/Target/Target.td
llvm/include/llvm/Target/TargetCallingConv.td
llvm/include/llvm/Target/TargetInstrPredicate.td
llvm/include/llvm/Target/TargetItinerary.td
llvm/include/llvm/Target/TargetPfmCounters.td
llvm/include/llvm/Target/TargetSchedule.td
llvm/include/llvm/Target/TargetSelectionDAG.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index 63a0713b736c..209925969df3 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -16,7 +16,7 @@
//------------------------------------------------------------------------------
class GenericInstruction : StandardPseudoInstruction {
- let isPreISelOpcode = 1;
+ let isPreISelOpcode = true;
}
// Provide a variant of an instruction with the same operands, but
@@ -31,8 +31,8 @@ class ConstrainedIntruction<GenericInstruction baseInst> :
// TODO: Do we need a better way to mark reads from FP mode than
// hasSideEffects?
- let hasSideEffects = 1;
- let mayRaiseFPException = 1;
+ let hasSideEffects = true;
+ let mayRaiseFPException = true;
}
// Extend the underlying scalar type of an operation, leaving the high bits
@@ -40,7 +40,7 @@ class ConstrainedIntruction<GenericInstruction baseInst> :
def G_ANYEXT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Sign extend the underlying scalar type of an operation, copying the sign bit
@@ -48,7 +48,7 @@ def G_ANYEXT : GenericInstruction {
def G_SEXT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Sign extend the a value from an arbitrary bit position, copying the sign bit
@@ -62,7 +62,7 @@ def G_SEXT : GenericInstruction {
def G_SEXT_INREG : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, untyped_imm_0:$sz);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Zero extend the underlying scalar type of an operation, putting zero bits
@@ -70,7 +70,7 @@ def G_SEXT_INREG : GenericInstruction {
def G_ZEXT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
@@ -79,150 +79,150 @@ def G_ZEXT : GenericInstruction {
def G_TRUNC : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_IMPLICIT_DEF : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_PHI : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins variable_ops);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_FRAME_INDEX : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_GLOBAL_VALUE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_INTTOPTR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_PTRTOINT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_BITCAST : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Only supports scalar result types
def G_CONSTANT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$imm);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Only supports scalar result types
def G_FCONSTANT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$imm);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_VASTART : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins type0:$list);
- let hasSideEffects = 0;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayStore = true;
}
def G_VAARG : GenericInstruction {
let OutOperandList = (outs type0:$val);
let InOperandList = (ins type1:$list, unknown:$align);
- let hasSideEffects = 0;
- let mayLoad = 1;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
+ let mayStore = true;
}
def G_CTLZ : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_CTLZ_ZERO_UNDEF : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_CTTZ : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_CTTZ_ZERO_UNDEF : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_CTPOP : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_BSWAP : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_BITREVERSE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_ADDRSPACE_CAST : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_BLOCK_ADDR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$ba);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_JUMP_TABLE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$jti);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_DYN_STACKALLOC : GenericInstruction {
let OutOperandList = (outs ptype0:$dst);
let InOperandList = (ins type1:$size, i32imm:$align);
- let hasSideEffects = 1;
+ let hasSideEffects = true;
}
def G_FREEZE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
//------------------------------------------------------------------------------
@@ -233,101 +233,101 @@ def G_FREEZE : GenericInstruction {
def G_ADD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic subtraction.
def G_SUB : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic multiplication.
def G_MUL : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic signed division.
def G_SDIV : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic unsigned division.
def G_UDIV : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic signed remainder.
def G_SREM : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic unsigned remainder.
def G_UREM : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic bitwise and.
def G_AND : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic bitwise or.
def G_OR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic bitwise xor.
def G_XOR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic left-shift.
def G_SHL : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic logical right-shift.
def G_LSHR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic arithmetic right-shift.
def G_ASHR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
/// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount.
@@ -335,7 +335,7 @@ def G_ASHR : GenericInstruction {
def G_FSHL : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2, type1:$src3);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
/// Funnel 'double' shifts take 3 operands, 2 inputs and the shift amount.
@@ -343,35 +343,35 @@ def G_FSHL : GenericInstruction {
def G_FSHR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2, type1:$src3);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic integer comparison.
def G_ICMP : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$tst, type1:$src1, type1:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic floating-point comparison.
def G_FCMP : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$tst, type1:$src1, type1:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic select
def G_SELECT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$tst, type0:$src1, type0:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic pointer offset.
def G_PTR_ADD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic pointer mask. type1 should be an integer with the same
@@ -379,46 +379,46 @@ def G_PTR_ADD : GenericInstruction {
def G_PTRMASK : GenericInstruction {
let OutOperandList = (outs ptype0:$dst);
let InOperandList = (ins ptype0:$src, type1:$bits);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic signed integer minimum.
def G_SMIN : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic signed integer maximum.
def G_SMAX : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic unsigned integer minimum.
def G_UMIN : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic unsigned integer maximum.
def G_UMAX : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic integer absolute value.
def G_ABS : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
//------------------------------------------------------------------------------
@@ -429,73 +429,73 @@ def G_ABS : GenericInstruction {
def G_UADDO : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic unsigned addition consuming and producing a carry flag.
def G_UADDE : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic signed addition producing a carry flag.
def G_SADDO : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic signed addition consuming and producing a carry flag.
def G_SADDE : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic unsigned subtraction producing a carry flag.
def G_USUBO : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic unsigned subtraction consuming and producing a carry flag.
def G_USUBE : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic signed subtraction producing a carry flag.
def G_SSUBO : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic signed subtraction consuming and producing a carry flag.
def G_SSUBE : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic unsigned multiplication producing a carry flag.
def G_UMULO : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic signed multiplication producing a carry flag.
def G_SMULO : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Multiply two numbers at twice the incoming bit width (unsigned) and return
@@ -503,8 +503,8 @@ def G_SMULO : GenericInstruction {
def G_UMULH : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Multiply two numbers at twice the incoming bit width (signed) and return
@@ -512,8 +512,8 @@ def G_UMULH : GenericInstruction {
def G_SMULH : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
//------------------------------------------------------------------------------
@@ -524,48 +524,48 @@ def G_SMULH : GenericInstruction {
def G_UADDSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic saturating signed addition.
def G_SADDSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic saturating unsigned subtraction.
def G_USUBSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic saturating signed subtraction.
def G_SSUBSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic saturating unsigned left shift.
def G_USHLSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic saturating signed left shift.
def G_SSHLSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type1:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
/// RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point
@@ -576,15 +576,15 @@ def G_SSHLSAT : GenericInstruction {
def G_SMULFIX : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
def G_UMULFIX : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
/// Same as the corresponding unsaturated fixed point instructions, but the
@@ -593,15 +593,15 @@ def G_UMULFIX : GenericInstruction {
def G_SMULFIXSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
def G_UMULFIXSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
/// RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on
@@ -611,15 +611,15 @@ def G_UMULFIXSAT : GenericInstruction {
def G_SDIVFIX : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
def G_UDIVFIX : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
/// Same as the corresponding unsaturated fixed point instructions,
@@ -628,15 +628,15 @@ def G_UDIVFIX : GenericInstruction {
def G_SDIVFIXSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
def G_UDIVFIXSAT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type0:$src1, untyped_imm_0:$scale);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
//------------------------------------------------------------------------------
@@ -646,61 +646,61 @@ def G_UDIVFIXSAT : GenericInstruction {
def G_FNEG : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_FPEXT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_FPTRUNC : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_FPTOSI : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_FPTOUI : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_SITOFP : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_UITOFP : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_FABS : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_FCOPYSIGN : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type1:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_FCANONICALIZE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two
@@ -713,15 +713,15 @@ def G_FCANONICALIZE : GenericInstruction {
def G_FMINNUM : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
def G_FMAXNUM : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimum or maximum on
@@ -731,15 +731,15 @@ def G_FMAXNUM : GenericInstruction {
def G_FMINNUM_IEEE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
def G_FMAXNUM_IEEE : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0
@@ -748,15 +748,15 @@ def G_FMAXNUM_IEEE : GenericInstruction {
def G_FMINIMUM : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
def G_FMAXIMUM : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
//------------------------------------------------------------------------------
@@ -767,24 +767,24 @@ def G_FMAXIMUM : GenericInstruction {
def G_FADD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic FP subtraction.
def G_FSUB : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic FP multiplication.
def G_FMUL : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
- let isCommutable = 1;
+ let hasSideEffects = false;
+ let isCommutable = true;
}
// Generic fused multiply-add instruction.
@@ -792,8 +792,8 @@ def G_FMUL : GenericInstruction {
def G_FMA : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
/// Generic FP multiply and add. Perform a * b + c, while getting the
@@ -801,92 +801,92 @@ def G_FMA : GenericInstruction {
def G_FMAD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2, type0:$src3);
- let hasSideEffects = 0;
- let isCommutable = 0;
+ let hasSideEffects = false;
+ let isCommutable = false;
}
// Generic FP division.
def G_FDIV : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic FP remainder.
def G_FREM : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point exponentiation.
def G_FPOW : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1, type0:$src2);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point exponentiation, with an integer power.
def G_FPOWI : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src0, type1:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point base-e exponential of a value.
def G_FEXP : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point base-2 exponential of a value.
def G_FEXP2 : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point base-e logarithm of a value.
def G_FLOG : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point base-2 logarithm of a value.
def G_FLOG2 : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point base-10 logarithm of a value.
def G_FLOG10 : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point ceiling of a value.
def G_FCEIL : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point cosine of a value.
def G_FCOS : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point sine of a value.
def G_FSIN : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point square root of a value.
@@ -896,28 +896,28 @@ def G_FSIN : GenericInstruction {
def G_FSQRT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point floor of a value.
def G_FFLOOR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point round to next integer.
def G_FRINT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Floating point round to the nearest integer.
def G_FNEARBYINT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
//------------------------------------------------------------------------------
@@ -926,31 +926,31 @@ def G_FNEARBYINT : GenericInstruction {
def G_INTRINSIC_TRUNC : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_INTRINSIC_ROUND : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_INTRINSIC_LRINT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_INTRINSIC_ROUNDEVEN : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_READCYCLECOUNTER : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins);
- let hasSideEffects = 1;
+ let hasSideEffects = true;
}
//------------------------------------------------------------------------------
@@ -965,24 +965,24 @@ def G_READCYCLECOUNTER : GenericInstruction {
def G_LOAD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins ptype1:$addr);
- let hasSideEffects = 0;
- let mayLoad = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
}
// Generic sign-extended load. Expects a MachineMemOperand in addition to explicit operands.
def G_SEXTLOAD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins ptype1:$addr);
- let hasSideEffects = 0;
- let mayLoad = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
}
// Generic zero-extended load. Expects a MachineMemOperand in addition to explicit operands.
def G_ZEXTLOAD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins ptype1:$addr);
- let hasSideEffects = 0;
- let mayLoad = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
}
// Generic indexed load. Combines a GEP with a load. $newaddr is set to $base + $offset.
@@ -991,32 +991,32 @@ def G_ZEXTLOAD : GenericInstruction {
def G_INDEXED_LOAD : GenericInstruction {
let OutOperandList = (outs type0:$dst, ptype1:$newaddr);
let InOperandList = (ins ptype1:$base, type2:$offset, unknown:$am);
- let hasSideEffects = 0;
- let mayLoad = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
}
// Same as G_INDEXED_LOAD except that the load performed is sign-extending, as with G_SEXTLOAD.
def G_INDEXED_SEXTLOAD : GenericInstruction {
let OutOperandList = (outs type0:$dst, ptype1:$newaddr);
let InOperandList = (ins ptype1:$base, type2:$offset, unknown:$am);
- let hasSideEffects = 0;
- let mayLoad = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
}
// Same as G_INDEXED_LOAD except that the load performed is zero-extending, as with G_ZEXTLOAD.
def G_INDEXED_ZEXTLOAD : GenericInstruction {
let OutOperandList = (outs type0:$dst, ptype1:$newaddr);
let InOperandList = (ins ptype1:$base, type2:$offset, unknown:$am);
- let hasSideEffects = 0;
- let mayLoad = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
}
// Generic store. Expects a MachineMemOperand in addition to explicit operands.
def G_STORE : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins type0:$src, ptype1:$addr);
- let hasSideEffects = 0;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayStore = true;
}
// Combines a store with a GEP. See description of G_INDEXED_LOAD for indexing behaviour.
@@ -1024,8 +1024,8 @@ def G_INDEXED_STORE : GenericInstruction {
let OutOperandList = (outs ptype0:$newaddr);
let InOperandList = (ins type1:$src, ptype0:$base, ptype2:$offset,
unknown:$am);
- let hasSideEffects = 0;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayStore = true;
}
// Generic atomic cmpxchg with internal success check. Expects a
@@ -1033,9 +1033,9 @@ def G_INDEXED_STORE : GenericInstruction {
def G_ATOMIC_CMPXCHG_WITH_SUCCESS : GenericInstruction {
let OutOperandList = (outs type0:$oldval, type1:$success);
let InOperandList = (ins type2:$addr, type0:$cmpval, type0:$newval);
- let hasSideEffects = 0;
- let mayLoad = 1;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
+ let mayStore = true;
}
// Generic atomic cmpxchg. Expects a MachineMemOperand in addition to explicit
@@ -1043,9 +1043,9 @@ def G_ATOMIC_CMPXCHG_WITH_SUCCESS : GenericInstruction {
def G_ATOMIC_CMPXCHG : GenericInstruction {
let OutOperandList = (outs type0:$oldval);
let InOperandList = (ins ptype1:$addr, type0:$cmpval, type0:$newval);
- let hasSideEffects = 0;
- let mayLoad = 1;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
+ let mayStore = true;
}
// Generic atomicrmw. Expects a MachineMemOperand in addition to explicit
@@ -1053,9 +1053,9 @@ def G_ATOMIC_CMPXCHG : GenericInstruction {
class G_ATOMICRMW_OP : GenericInstruction {
let OutOperandList = (outs type0:$oldval);
let InOperandList = (ins ptype1:$addr, type0:$val);
- let hasSideEffects = 0;
- let mayLoad = 1;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
+ let mayStore = true;
}
def G_ATOMICRMW_XCHG : G_ATOMICRMW_OP;
@@ -1075,7 +1075,7 @@ def G_ATOMICRMW_FSUB : G_ATOMICRMW_OP;
def G_FENCE : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$ordering, i32imm:$scope);
- let hasSideEffects = 1;
+ let hasSideEffects = true;
}
//------------------------------------------------------------------------------
@@ -1088,7 +1088,7 @@ def G_FENCE : GenericInstruction {
def G_EXTRACT : GenericInstruction {
let OutOperandList = (outs type0:$res);
let InOperandList = (ins type1:$src, untyped_imm_0:$offset);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Extract multiple registers specified size, starting from blocks given by
@@ -1100,14 +1100,14 @@ def G_EXTRACT : GenericInstruction {
def G_UNMERGE_VALUES : GenericInstruction {
let OutOperandList = (outs type0:$dst0, variable_ops);
let InOperandList = (ins type1:$src);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Insert a smaller register into a larger one at the specified bit-index.
def G_INSERT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, type1:$op, untyped_imm_0:$offset);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Concatenate multiple registers of the same size into a wider register.
@@ -1117,7 +1117,7 @@ def G_INSERT : GenericInstruction {
def G_MERGE_VALUES : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src0, variable_ops);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
/// Create a vector from multiple scalar registers. No implicit
@@ -1126,7 +1126,7 @@ def G_MERGE_VALUES : GenericInstruction {
def G_BUILD_VECTOR : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src0, variable_ops);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
/// Like G_BUILD_VECTOR, but truncates the larger operand types to fit the
@@ -1134,21 +1134,21 @@ def G_BUILD_VECTOR : GenericInstruction {
def G_BUILD_VECTOR_TRUNC : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src0, variable_ops);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
/// Create a vector by concatenating vectors together.
def G_CONCAT_VECTORS : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src0, variable_ops);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Intrinsic without side effects.
def G_INTRINSIC : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins unknown:$intrin, variable_ops);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
// Conservatively assume this is convergent. If there turnes out to
// be a need, there should be separate convergent intrinsic opcodes.
@@ -1159,13 +1159,13 @@ def G_INTRINSIC : GenericInstruction {
def G_INTRINSIC_W_SIDE_EFFECTS : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins unknown:$intrin, variable_ops);
- let hasSideEffects = 1;
- let mayLoad = 1;
- let mayStore = 1;
+ let hasSideEffects = true;
+ let mayLoad = true;
+ let mayStore = true;
// Conservatively assume this is convergent. If there turnes out to
// be a need, there should be separate convergent intrinsic opcodes.
- let isConvergent = 1;
+ let isConvergent = true;
}
//------------------------------------------------------------------------------
@@ -1176,61 +1176,61 @@ def G_INTRINSIC_W_SIDE_EFFECTS : GenericInstruction {
def G_BR : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins unknown:$src1);
- let hasSideEffects = 0;
- let isBranch = 1;
- let isTerminator = 1;
- let isBarrier = 1;
+ let hasSideEffects = false;
+ let isBranch = true;
+ let isTerminator = true;
+ let isBarrier = true;
}
// Generic conditional branch.
def G_BRCOND : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins type0:$tst, unknown:$truebb);
- let hasSideEffects = 0;
- let isBranch = 1;
- let isTerminator = 1;
+ let hasSideEffects = false;
+ let isBranch = true;
+ let isTerminator = true;
}
// Generic indirect branch.
def G_BRINDIRECT : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins type0:$src1);
- let hasSideEffects = 0;
- let isBranch = 1;
- let isTerminator = 1;
- let isBarrier = 1;
- let isIndirectBranch = 1;
+ let hasSideEffects = false;
+ let isBranch = true;
+ let isTerminator = true;
+ let isBarrier = true;
+ let isIndirectBranch = true;
}
// Generic branch to jump table entry
def G_BRJT : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins ptype0:$tbl, unknown:$jti, type1:$idx);
- let hasSideEffects = 0;
- let isBranch = 1;
- let isTerminator = 1;
- let isBarrier = 1;
- let isIndirectBranch = 1;
+ let hasSideEffects = false;
+ let isBranch = true;
+ let isTerminator = true;
+ let isBarrier = true;
+ let isIndirectBranch = true;
}
def G_READ_REGISTER : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins unknown:$register);
- let hasSideEffects = 1;
+ let hasSideEffects = true;
// Assume convergent. It's probably not worth the effort of somehow
// modeling convergent and nonconvergent register accesses.
- let isConvergent = 1;
+ let isConvergent = true;
}
def G_WRITE_REGISTER : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins unknown:$register, type0:$value);
- let hasSideEffects = 1;
+ let hasSideEffects = true;
// Assume convergent. It's probably not worth the effort of somehow
// modeling convergent and nonconvergent register accesses.
- let isConvergent = 1;
+ let isConvergent = true;
}
//------------------------------------------------------------------------------
@@ -1241,14 +1241,14 @@ def G_WRITE_REGISTER : GenericInstruction {
def G_INSERT_VECTOR_ELT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type0:$src, type1:$elt, type2:$idx);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic extractelement.
def G_EXTRACT_VECTOR_ELT : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$src, type2:$idx);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
// Generic shufflevector.
@@ -1258,7 +1258,7 @@ def G_EXTRACT_VECTOR_ELT : GenericInstruction {
def G_SHUFFLE_VECTOR: GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$v1, type1:$v2, unknown:$mask);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
//------------------------------------------------------------------------------
@@ -1268,19 +1268,19 @@ def G_SHUFFLE_VECTOR: GenericInstruction {
class VectorReduction : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$v);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_VECREDUCE_SEQ_FADD : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$acc, type2:$v);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_VECREDUCE_SEQ_FMUL : GenericInstruction {
let OutOperandList = (outs type0:$dst);
let InOperandList = (ins type1:$acc, type2:$v);
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def G_VECREDUCE_FADD : VectorReduction;
@@ -1318,22 +1318,22 @@ def G_STRICT_FSQRT : ConstrainedIntruction<G_FSQRT>;
def G_MEMCPY : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins ptype0:$dst_addr, ptype1:$src_addr, type2:$size, untyped_imm_0:$tailcall);
- let hasSideEffects = 0;
- let mayLoad = 1;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
+ let mayStore = true;
}
def G_MEMMOVE : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins ptype0:$dst_addr, ptype1:$src_addr, type2:$size, untyped_imm_0:$tailcall);
- let hasSideEffects = 0;
- let mayLoad = 1;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayLoad = true;
+ let mayStore = true;
}
def G_MEMSET : GenericInstruction {
let OutOperandList = (outs);
let InOperandList = (ins ptype0:$dst_addr, type1:$value, type2:$size, untyped_imm_0:$tailcall);
- let hasSideEffects = 0;
- let mayStore = 1;
+ let hasSideEffects = false;
+ let mayStore = true;
}
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index c8715f01defd..ff4cf3a5d98d 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -26,8 +26,8 @@ class GINodeEquiv<Instruction i, SDNode node> {
// SelectionDAG has separate nodes for atomic and non-atomic memory operations
// (ISD::LOAD, ISD::ATOMIC_LOAD, ISD::STORE, ISD::ATOMIC_STORE) but GlobalISel
// stores this information in the MachineMemoryOperand.
- bit CheckMMOIsNonAtomic = 0;
- bit CheckMMOIsAtomic = 0;
+ bit CheckMMOIsNonAtomic = false;
+ bit CheckMMOIsAtomic = false;
// SelectionDAG has one node for all loads and uses predicates to
//
diff erentiate them. GlobalISel on the other hand uses separate opcodes.
@@ -158,7 +158,7 @@ def : GINodeEquiv<G_STRICT_FSQRT, strict_fsqrt>;
// separate nodes for them. This GINodeEquiv maps the non-atomic loads to
// G_LOAD with a non-atomic MachineMemOperand.
def : GINodeEquiv<G_LOAD, ld> {
- let CheckMMOIsNonAtomic = 1;
+ let CheckMMOIsNonAtomic = true;
let IfSignExtend = G_SEXTLOAD;
let IfZeroExtend = G_ZEXTLOAD;
}
@@ -174,17 +174,17 @@ def : GINodeEquiv<G_ICMP, setcc> {
// G_STORE handles both atomic and non-atomic stores where as SelectionDAG had
// separate nodes for them. This GINodeEquiv maps the non-atomic stores to
// G_STORE with a non-atomic MachineMemOperand.
-def : GINodeEquiv<G_STORE, st> { let CheckMMOIsNonAtomic = 1; }
+def : GINodeEquiv<G_STORE, st> { let CheckMMOIsNonAtomic = true; }
def : GINodeEquiv<G_LOAD, atomic_load> {
- let CheckMMOIsNonAtomic = 0;
- let CheckMMOIsAtomic = 1;
+ let CheckMMOIsNonAtomic = false;
+ let CheckMMOIsAtomic = true;
}
// Operands are swapped for atomic_store vs. regular store
def : GINodeEquiv<G_STORE, atomic_store> {
- let CheckMMOIsNonAtomic = 0;
- let CheckMMOIsAtomic = 1;
+ let CheckMMOIsNonAtomic = false;
+ let CheckMMOIsAtomic = true;
}
def : GINodeEquiv<G_ATOMIC_CMPXCHG, atomic_cmp_swap>;
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 8fba826f2187..96fbfcc1f381 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -110,9 +110,9 @@ class SubRegIndex<int size, int offset = 0> {
// ComposedSubRegIndex - A sub-register that is the result of composing A and B.
// Offset is set to the sum of A and B's Offsets. Size is set to B's Size.
class ComposedSubRegIndex<SubRegIndex A, SubRegIndex B>
- : SubRegIndex<B.Size, !if(!eq(A.Offset, -1), -1,
- !if(!eq(B.Offset, -1), -1,
- !add(A.Offset, B.Offset)))> {
+ : SubRegIndex<B.Size, !cond(!eq(A.Offset, -1): -1,
+ !eq(B.Offset, -1): -1,
+ true: !add(A.Offset, B.Offset))> {
// See SubRegIndex.
let ComposedOf = [A, B];
}
@@ -175,12 +175,12 @@ class Register<string n, list<string> altNames = []> {
// completely determined by the value of its sub-registers. For example, the
// x86 register AX is covered by its sub-registers AL and AH, but EAX is not
// covered by its sub-register AX.
- bit CoveredBySubRegs = 0;
+ bit CoveredBySubRegs = false;
// HWEncoding - The target specific hardware encoding for this register.
bits<16> HWEncoding = 0;
- bit isArtificial = 0;
+ bit isArtificial = false;
}
// RegisterWithSubRegs - This can be used to define instances of Register which
@@ -252,7 +252,7 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
// isAllocatable - Specify that the register class can be used for virtual
// registers and register allocation. Some register classes are only used to
// model instruction operand constraints, and should have isAllocatable = 0.
- bit isAllocatable = 1;
+ bit isAllocatable = true;
// AltOrders - List of alternative allocation orders. The default order is
// MemberList itself, and that is good enough for most targets since the
@@ -278,7 +278,7 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
// Generate register pressure set for this register class and any class
// synthesized from it. Set to 0 to inhibit unneeded pressure sets.
- bit GeneratePressureSet = 1;
+ bit GeneratePressureSet = true;
// Weight override for register pressure calculation. This is the value
// TargetRegisterClass::getRegClassWeight() will return. The weight is in
@@ -452,7 +452,7 @@ class InstructionEncoding {
// DecodeInstB() is not able to determine if all possible values of ?? are
// valid or not. If DecodeInstB() returns Fail the decoder will attempt to
// decode the bitpattern as InstA too.
- bit hasCompleteDecoder = 1;
+ bit hasCompleteDecoder = true;
}
// Allows specifying an InstructionEncoding by HwMode. If an Instruction specifies
@@ -506,59 +506,59 @@ class Instruction : InstructionEncoding {
// Indicates if this is a pre-isel opcode that should be
// legalized/regbankselected/selected.
- bit isPreISelOpcode = 0;
+ bit isPreISelOpcode = false;
// These bits capture information about the high-level semantics of the
// instruction.
- bit isReturn = 0; // Is this instruction a return instruction?
- bit isBranch = 0; // Is this instruction a branch instruction?
- bit isEHScopeReturn = 0; // Does this instruction end an EH scope?
- bit isIndirectBranch = 0; // Is this instruction an indirect branch?
- bit isCompare = 0; // Is this instruction a comparison instruction?
- bit isMoveImm = 0; // Is this instruction a move immediate instruction?
- bit isMoveReg = 0; // Is this instruction a move register instruction?
- bit isBitcast = 0; // Is this instruction a bitcast instruction?
- bit isSelect = 0; // Is this instruction a select instruction?
- bit isBarrier = 0; // Can control flow fall through this instruction?
- bit isCall = 0; // Is this instruction a call instruction?
- bit isAdd = 0; // Is this instruction an add instruction?
- bit isTrap = 0; // Is this instruction a trap instruction?
- bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand?
- bit mayLoad = ?; // Is it possible for this inst to read memory?
- bit mayStore = ?; // Is it possible for this inst to write memory?
- bit mayRaiseFPException = 0; // Can this raise a floating-point exception?
- bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
- bit isCommutable = 0; // Is this 3 operand instruction commutable?
- bit isTerminator = 0; // Is this part of the terminator for a basic block?
- bit isReMaterializable = 0; // Is this instruction re-materializable?
- bit isPredicable = 0; // 1 means this instruction is predicable
- // even if it does not have any operand
- // tablegen can identify as a predicate
- bit isUnpredicable = 0; // 1 means this instruction is not predicable
- // even if it _does_ have a predicate operand
- bit hasDelaySlot = 0; // Does this instruction have an delay slot?
- bit usesCustomInserter = 0; // Pseudo instr needing special help.
- bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
- bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
- bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
- bit isConvergent = 0; // Is this instruction convergent?
- bit isAuthenticated = 0; // Does this instruction authenticate a pointer?
- bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
- bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
- bit hasExtraDefRegAllocReq = 0; // Defs have special regalloc requirement?
- bit isRegSequence = 0; // Is this instruction a kind of reg sequence?
- // If so, make sure to override
- // TargetInstrInfo::getRegSequenceLikeInputs.
- bit isPseudo = 0; // Is this instruction a pseudo-instruction?
- // If so, won't have encoding information for
- // the [MC]CodeEmitter stuff.
- bit isExtractSubreg = 0; // Is this instruction a kind of extract subreg?
- // If so, make sure to override
- // TargetInstrInfo::getExtractSubregLikeInputs.
- bit isInsertSubreg = 0; // Is this instruction a kind of insert subreg?
- // If so, make sure to override
- // TargetInstrInfo::getInsertSubregLikeInputs.
- bit variadicOpsAreDefs = 0; // Are variadic operands definitions?
+ bit isReturn = false; // Is this instruction a return instruction?
+ bit isBranch = false; // Is this instruction a branch instruction?
+ bit isEHScopeReturn = false; // Does this instruction end an EH scope?
+ bit isIndirectBranch = false; // Is this instruction an indirect branch?
+ bit isCompare = false; // Is this instruction a comparison instruction?
+ bit isMoveImm = false; // Is this instruction a move immediate instruction?
+ bit isMoveReg = false; // Is this instruction a move register instruction?
+ bit isBitcast = false; // Is this instruction a bitcast instruction?
+ bit isSelect = false; // Is this instruction a select instruction?
+ bit isBarrier = false; // Can control flow fall through this instruction?
+ bit isCall = false; // Is this instruction a call instruction?
+ bit isAdd = false; // Is this instruction an add instruction?
+ bit isTrap = false; // Is this instruction a trap instruction?
+ bit canFoldAsLoad = false; // Can this be folded as a simple memory operand?
+ bit mayLoad = ?; // Is it possible for this inst to read memory?
+ bit mayStore = ?; // Is it possible for this inst to write memory?
+ bit mayRaiseFPException = false; // Can this raise a floating-point exception?
+ bit isConvertibleToThreeAddress = false; // Can this 2-addr instruction promote?
+ bit isCommutable = false; // Is this 3 operand instruction commutable?
+ bit isTerminator = false; // Is this part of the terminator for a basic block?
+ bit isReMaterializable = false; // Is this instruction re-materializable?
+ bit isPredicable = false; // 1 means this instruction is predicable
+ // even if it does not have any operand
+ // tablegen can identify as a predicate
+ bit isUnpredicable = false; // 1 means this instruction is not predicable
+ // even if it _does_ have a predicate operand
+ bit hasDelaySlot = false; // Does this instruction have an delay slot?
+ bit usesCustomInserter = false; // Pseudo instr needing special help.
+ bit hasPostISelHook = false; // To be *adjusted* after isel by target hook.
+ bit hasCtrlDep = false; // Does this instruction r/w ctrl-flow chains?
+ bit isNotDuplicable = false; // Is it unsafe to duplicate this instruction?
+ bit isConvergent = false; // Is this instruction convergent?
+ bit isAuthenticated = false; // Does this instruction authenticate a pointer?
+ bit isAsCheapAsAMove = false; // As cheap (or cheaper) than a move instruction.
+ bit hasExtraSrcRegAllocReq = false; // Sources have special regalloc requirement?
+ bit hasExtraDefRegAllocReq = false; // Defs have special regalloc requirement?
+ bit isRegSequence = false; // Is this instruction a kind of reg sequence?
+ // If so, make sure to override
+ // TargetInstrInfo::getRegSequenceLikeInputs.
+ bit isPseudo = false; // Is this instruction a pseudo-instruction?
+ // If so, won't have encoding information for
+ // the [MC]CodeEmitter stuff.
+ bit isExtractSubreg = false; // Is this instruction a kind of extract subreg?
+ // If so, make sure to override
+ // TargetInstrInfo::getExtractSubregLikeInputs.
+ bit isInsertSubreg = false; // Is this instruction a kind of insert subreg?
+ // If so, make sure to override
+ // TargetInstrInfo::getInsertSubregLikeInputs.
+ bit variadicOpsAreDefs = false; // Are variadic operands definitions?
// Does the instruction have side effects that are not captured by any
// operands of the instruction or other flags?
@@ -581,15 +581,15 @@ class Instruction : InstructionEncoding {
// CodeEmitter unchanged, but duplicates a canonical instruction
// definition's encoding and should be ignored when constructing the
// assembler match tables.
- bit isCodeGenOnly = 0;
+ bit isCodeGenOnly = false;
// Is this instruction a pseudo instruction for use by the assembler parser.
- bit isAsmParserOnly = 0;
+ bit isAsmParserOnly = false;
// This instruction is not expected to be queried for scheduling latencies
// and therefore needs no scheduling information even for a complete
// scheduling model.
- bit hasNoSchedulingInfo = 0;
+ bit hasNoSchedulingInfo = false;
InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
@@ -630,13 +630,13 @@ class Instruction : InstructionEncoding {
/// UseNamedOperandTable - If set, the operand indices of this instruction
/// can be queried via the getNamedOperandIdx() function which is generated
/// by TableGen.
- bit UseNamedOperandTable = 0;
+ bit UseNamedOperandTable = false;
/// Should FastISel ignore this instruction. For certain ISAs, they have
/// instructions which map to the same ISD Opcode, value type operands and
/// instruction selection predicates. FastISel cannot handle such cases, but
/// SelectionDAG can.
- bit FastISelShouldIgnore = 0;
+ bit FastISelShouldIgnore = false;
}
/// Defines an additional encoding that disassembles to the given instruction
@@ -651,7 +651,7 @@ class AdditionalEncoding<Instruction I> : InstructionEncoding {
/// pseudo.
class PseudoInstExpansion<dag Result> {
dag ResultInst = Result; // The instruction to generate.
- bit isPseudo = 1;
+ bit isPseudo = true;
}
/// Predicates - These are extra conditionals which are turned into instruction
@@ -662,7 +662,7 @@ class Predicate<string cond> {
/// AssemblerMatcherPredicate - If this feature can be used by the assembler
/// matcher, this is true. Targets should set this by inheriting their
/// feature from the AssemblerPredicate class in addition to Predicate.
- bit AssemblerMatcherPredicate = 0;
+ bit AssemblerMatcherPredicate = false;
/// AssemblerCondDag - Set of subtarget features being tested used
/// as alternative condition string used for assembler matcher. Must be used
@@ -688,7 +688,7 @@ class Predicate<string cond> {
/// every function change. Most predicates can leave this at '0'.
///
/// Ignored by SelectionDAG, it always recomputes the predicate on every use.
- bit RecomputePerFunction = 0;
+ bit RecomputePerFunction = false;
}
/// NoHonorSignDependentRounding - This predicate is true if support for
@@ -788,7 +788,7 @@ class AsmOperandClass {
/// marked as IsOptional.
///
/// Optional arguments must be at the end of the operand list.
- bit IsOptional = 0;
+ bit IsOptional = false;
/// The name of the method on the target specific asm parser that returns the
/// default operand for this optional operand. This method is only used if
@@ -809,7 +809,7 @@ class Operand<ValueType ty> : DAGOperand {
ValueType Type = ty;
string PrintMethod = "printOperand";
string EncoderMethod = "";
- bit hasCompleteDecoder = 1;
+ bit hasCompleteDecoder = true;
string OperandType = "OPERAND_UNKNOWN";
dag MIOperandInfo = (ops);
@@ -877,8 +877,8 @@ def f64imm : Operand<f64>;
// have the same LLT).
class TypedOperand<string Ty> : Operand<untyped> {
let OperandType = Ty;
- bit IsPointer = 0;
- bit IsImmediate = 0;
+ bit IsPointer = false;
+ bit IsImmediate = false;
}
def type0 : TypedOperand<"OPERAND_GENERIC_0">;
@@ -888,7 +888,7 @@ def type3 : TypedOperand<"OPERAND_GENERIC_3">;
def type4 : TypedOperand<"OPERAND_GENERIC_4">;
def type5 : TypedOperand<"OPERAND_GENERIC_5">;
-let IsPointer = 1 in {
+let IsPointer = true in {
def ptype0 : TypedOperand<"OPERAND_GENERIC_0">;
def ptype1 : TypedOperand<"OPERAND_GENERIC_1">;
def ptype2 : TypedOperand<"OPERAND_GENERIC_2">;
@@ -900,7 +900,7 @@ let IsPointer = 1 in {
// untyped_imm is for operands where isImm() will be true. It currently has no
// special behaviour and is only used for clarity.
def untyped_imm_0 : TypedOperand<"OPERAND_GENERIC_IMM_0"> {
- let IsImmediate = 1;
+ let IsImmediate = true;
}
/// zero_reg definition - Special node to stand for the zero register.
@@ -952,7 +952,7 @@ class InstrInfo {
// For instance, while both Sparc and PowerPC are big-endian platforms, the
// Sparc manual specifies its instructions in the format [31..0] (big), while
// PowerPC specifies them using the format [0..31] (little).
- bit isLittleEndianEncoding = 0;
+ bit isLittleEndianEncoding = false;
// The instruction properties mayLoad, mayStore, and hasSideEffects are unset
// by default, and TableGen will infer their value from the instruction
@@ -963,7 +963,7 @@ class InstrInfo {
// is set, it will guess a safe value instead.
//
// This option is a temporary migration help. It will go away.
- bit guessInstructionProperties = 1;
+ bit guessInstructionProperties = true;
// TableGen's instruction encoder generator has support for matching operands
// to bit-field variables both by name and by position. While matching by
@@ -975,7 +975,7 @@ class InstrInfo {
// This option is temporary; it will go away once the TableGen decoder
// generator has better support for complex operands and targets have
// migrated away from using positionally encoded operands.
- bit decodePositionallyEncodedOperands = 0;
+ bit decodePositionallyEncodedOperands = false;
// When set, this indicates that there will be no overlap between those
// operands that are matched by ordering (positional operands) and those
@@ -984,7 +984,7 @@ class InstrInfo {
// This option is temporary; it will go away once the TableGen decoder
// generator has better support for complex operands and targets have
// migrated away from using positionally encoded operands.
- bit noNamedPositionallyEncodedOperands = 0;
+ bit noNamedPositionallyEncodedOperands = false;
}
// Standard Pseudo Instructions.
@@ -994,31 +994,31 @@ class InstrInfo {
// targets that set guessInstructionProperties=0. Any local definition of
// mayLoad/mayStore takes precedence over these default values.
class StandardPseudoInstruction : Instruction {
- let mayLoad = 0;
- let mayStore = 0;
- let isCodeGenOnly = 1;
- let isPseudo = 1;
- let hasNoSchedulingInfo = 1;
+ let mayLoad = false;
+ let mayStore = false;
+ let isCodeGenOnly = true;
+ let isPseudo = true;
+ let hasNoSchedulingInfo = true;
let Namespace = "TargetOpcode";
}
def PHI : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins variable_ops);
let AsmString = "PHINODE";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def INLINEASM : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "";
- let hasSideEffects = 0; // Note side effect is encoded in an operand.
+ let hasSideEffects = false; // Note side effect is encoded in an operand.
}
def INLINEASM_BR : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "";
// Unlike INLINEASM, this is always treated as having side-effects.
- let hasSideEffects = 1;
+ let hasSideEffects = true;
// Despite potentially branching, this instruction is intentionally _not_
// marked as a terminator or a branch.
}
@@ -1026,170 +1026,170 @@ def CFI_INSTRUCTION : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "";
- let hasCtrlDep = 1;
- let hasSideEffects = 0;
- let isNotDuplicable = 1;
+ let hasCtrlDep = true;
+ let hasSideEffects = false;
+ let isNotDuplicable = true;
}
def EH_LABEL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "";
- let hasCtrlDep = 1;
- let hasSideEffects = 0;
- let isNotDuplicable = 1;
+ let hasCtrlDep = true;
+ let hasSideEffects = false;
+ let isNotDuplicable = true;
}
def GC_LABEL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "";
- let hasCtrlDep = 1;
- let hasSideEffects = 0;
- let isNotDuplicable = 1;
+ let hasCtrlDep = true;
+ let hasSideEffects = false;
+ let isNotDuplicable = true;
}
def ANNOTATION_LABEL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "";
- let hasCtrlDep = 1;
- let hasSideEffects = 0;
- let isNotDuplicable = 1;
+ let hasCtrlDep = true;
+ let hasSideEffects = false;
+ let isNotDuplicable = true;
}
def KILL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def EXTRACT_SUBREG : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$supersrc, i32imm:$subidx);
let AsmString = "";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def INSERT_SUBREG : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$supersrc, unknown:$subsrc, i32imm:$subidx);
let AsmString = "";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
let Constraints = "$supersrc = $dst";
}
def IMPLICIT_DEF : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins);
let AsmString = "";
- let hasSideEffects = 0;
- let isReMaterializable = 1;
- let isAsCheapAsAMove = 1;
+ let hasSideEffects = false;
+ let isReMaterializable = true;
+ let isAsCheapAsAMove = true;
}
def SUBREG_TO_REG : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$implsrc, unknown:$subsrc, i32imm:$subidx);
let AsmString = "";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def COPY_TO_REGCLASS : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$src, i32imm:$regclass);
let AsmString = "";
- let hasSideEffects = 0;
- let isAsCheapAsAMove = 1;
+ let hasSideEffects = false;
+ let isAsCheapAsAMove = true;
}
def DBG_VALUE : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "DBG_VALUE";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def DBG_INSTR_REF : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "DBG_INSTR_REF";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def DBG_LABEL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins unknown:$label);
let AsmString = "DBG_LABEL";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def REG_SEQUENCE : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$supersrc, variable_ops);
let AsmString = "";
- let hasSideEffects = 0;
- let isAsCheapAsAMove = 1;
+ let hasSideEffects = false;
+ let isAsCheapAsAMove = true;
}
def COPY : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins unknown:$src);
let AsmString = "";
- let hasSideEffects = 0;
- let isAsCheapAsAMove = 1;
- let hasNoSchedulingInfo = 0;
+ let hasSideEffects = false;
+ let isAsCheapAsAMove = true;
+ let hasNoSchedulingInfo = false;
}
def BUNDLE : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "BUNDLE";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def LIFETIME_START : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "LIFETIME_START";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def LIFETIME_END : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$id);
let AsmString = "LIFETIME_END";
- let hasSideEffects = 0;
+ let hasSideEffects = false;
}
def STACKMAP : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i64imm:$id, i32imm:$nbytes, variable_ops);
- let hasSideEffects = 1;
- let isCall = 1;
- let mayLoad = 1;
- let usesCustomInserter = 1;
+ let hasSideEffects = true;
+ let isCall = true;
+ let mayLoad = true;
+ let usesCustomInserter = true;
}
def PATCHPOINT : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins i64imm:$id, i32imm:$nbytes, unknown:$callee,
i32imm:$nargs, i32imm:$cc, variable_ops);
- let hasSideEffects = 1;
- let isCall = 1;
- let mayLoad = 1;
- let usesCustomInserter = 1;
+ let hasSideEffects = true;
+ let isCall = true;
+ let mayLoad = true;
+ let usesCustomInserter = true;
}
def STATEPOINT : StandardPseudoInstruction {
let OutOperandList = (outs variable_ops);
let InOperandList = (ins variable_ops);
- let usesCustomInserter = 1;
- let mayLoad = 1;
- let mayStore = 1;
- let hasSideEffects = 1;
- let isCall = 1;
+ let usesCustomInserter = true;
+ let mayLoad = true;
+ let mayStore = true;
+ let hasSideEffects = true;
+ let isCall = true;
}
def LOAD_STACK_GUARD : StandardPseudoInstruction {
let OutOperandList = (outs ptr_rc:$dst);
let InOperandList = (ins);
- let mayLoad = 1;
- bit isReMaterializable = 1;
- let hasSideEffects = 0;
- bit isPseudo = 1;
+ let mayLoad = true;
+ bit isReMaterializable = true;
+ let hasSideEffects = false;
+ bit isPseudo = true;
}
def PREALLOCATED_SETUP : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins i32imm:$a);
- let usesCustomInserter = 1;
- let hasSideEffects = 1;
+ let usesCustomInserter = true;
+ let hasSideEffects = true;
}
def PREALLOCATED_ARG : StandardPseudoInstruction {
let OutOperandList = (outs ptr_rc:$loc);
let InOperandList = (ins i32imm:$a, i32imm:$b);
- let usesCustomInserter = 1;
- let hasSideEffects = 1;
+ let usesCustomInserter = true;
+ let hasSideEffects = true;
}
def LOCAL_ESCAPE : StandardPseudoInstruction {
// This instruction is really just a label. It has to be part of the chain so
@@ -1197,93 +1197,93 @@ def LOCAL_ESCAPE : StandardPseudoInstruction {
// no side effects.
let OutOperandList = (outs);
let InOperandList = (ins ptr_rc:$symbol, i32imm:$id);
- let hasSideEffects = 0;
- let hasCtrlDep = 1;
+ let hasSideEffects = false;
+ let hasCtrlDep = true;
}
def FAULTING_OP : StandardPseudoInstruction {
let OutOperandList = (outs unknown:$dst);
let InOperandList = (ins variable_ops);
- let usesCustomInserter = 1;
- let hasSideEffects = 1;
- let mayLoad = 1;
- let mayStore = 1;
- let isTerminator = 1;
- let isBranch = 1;
+ let usesCustomInserter = true;
+ let hasSideEffects = true;
+ let mayLoad = true;
+ let mayStore = true;
+ let isTerminator = true;
+ let isBranch = true;
}
def PATCHABLE_OP : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
- let usesCustomInserter = 1;
- let mayLoad = 1;
- let mayStore = 1;
- let hasSideEffects = 1;
+ let usesCustomInserter = true;
+ let mayLoad = true;
+ let mayStore = true;
+ let hasSideEffects = true;
}
def PATCHABLE_FUNCTION_ENTER : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins);
let AsmString = "# XRay Function Enter.";
- let usesCustomInserter = 1;
- let hasSideEffects = 1;
+ let usesCustomInserter = true;
+ let hasSideEffects = true;
}
def PATCHABLE_RET : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "# XRay Function Patchable RET.";
- let usesCustomInserter = 1;
- let hasSideEffects = 1;
- let isTerminator = 1;
- let isReturn = 1;
+ let usesCustomInserter = true;
+ let hasSideEffects = true;
+ let isTerminator = true;
+ let isReturn = true;
}
def PATCHABLE_FUNCTION_EXIT : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins);
let AsmString = "# XRay Function Exit.";
- let usesCustomInserter = 1;
- let hasSideEffects = 1;
- let isReturn = 0; // Original return instruction will follow
+ let usesCustomInserter = true;
+ let hasSideEffects = true;
+ let isReturn = false; // Original return instruction will follow
}
def PATCHABLE_TAIL_CALL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "# XRay Tail Call Exit.";
- let usesCustomInserter = 1;
- let hasSideEffects = 1;
- let isReturn = 1;
+ let usesCustomInserter = true;
+ let hasSideEffects = true;
+ let isReturn = true;
}
def PATCHABLE_EVENT_CALL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins ptr_rc:$event, unknown:$size);
let AsmString = "# XRay Custom Event Log.";
- let usesCustomInserter = 1;
- let isCall = 1;
- let mayLoad = 1;
- let mayStore = 1;
- let hasSideEffects = 1;
+ let usesCustomInserter = true;
+ let isCall = true;
+ let mayLoad = true;
+ let mayStore = true;
+ let hasSideEffects = true;
}
def PATCHABLE_TYPED_EVENT_CALL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins unknown:$type, ptr_rc:$event, unknown:$size);
let AsmString = "# XRay Typed Event Log.";
- let usesCustomInserter = 1;
- let isCall = 1;
- let mayLoad = 1;
- let mayStore = 1;
- let hasSideEffects = 1;
+ let usesCustomInserter = true;
+ let isCall = true;
+ let mayLoad = true;
+ let mayStore = true;
+ let hasSideEffects = true;
}
def FENTRY_CALL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins);
let AsmString = "# FEntry call";
- let usesCustomInserter = 1;
- let mayLoad = 1;
- let mayStore = 1;
- let hasSideEffects = 1;
+ let usesCustomInserter = true;
+ let mayLoad = true;
+ let mayStore = true;
+ let hasSideEffects = true;
}
def ICALL_BRANCH_FUNNEL : StandardPseudoInstruction {
let OutOperandList = (outs);
let InOperandList = (ins variable_ops);
let AsmString = "";
- let hasSideEffects = 1;
+ let hasSideEffects = true;
}
// Generic opcodes used in GlobalISel.
@@ -1309,7 +1309,7 @@ class AsmParser {
// ShouldEmitMatchRegisterName - Set to false if the target needs a hand
// written register name matcher
- bit ShouldEmitMatchRegisterName = 1;
+ bit ShouldEmitMatchRegisterName = true;
// Set to true if the target needs a generated 'alternative register name'
// matcher.
@@ -1317,7 +1317,7 @@ class AsmParser {
// This generates a function which can be used to lookup registers from
// their aliases. This function will fail when called on targets where
// several registers share the same alias (i.e. not a 1:1 mapping).
- bit ShouldEmitMatchRegisterAltName = 0;
+ bit ShouldEmitMatchRegisterAltName = false;
// Set to true if MatchRegisterName and MatchRegisterAltName functions
// should be generated even if there are duplicate register names. The
@@ -1325,11 +1325,11 @@ class AsmParser {
// (e.g. in validateTargetOperandClass), and there are no guarantees about
// which numeric register identifier will be returned in the case of
// multiple matches.
- bit AllowDuplicateRegisterNames = 0;
+ bit AllowDuplicateRegisterNames = false;
// HasMnemonicFirst - Set to false if target instructions don't always
// start with a mnemonic as the first token.
- bit HasMnemonicFirst = 1;
+ bit HasMnemonicFirst = true;
// ReportMultipleNearMisses -
// When 0, the assembly matcher reports an error for one encoding or operand
@@ -1337,7 +1337,7 @@ class AsmParser {
// When 1, the assembly matcher returns a list of encodings that were close
// to matching the parsed instruction, so to allow more detailed error
// messages.
- bit ReportMultipleNearMisses = 0;
+ bit ReportMultipleNearMisses = false;
}
def DefaultAsmParser : AsmParser;
@@ -1348,7 +1348,7 @@ def DefaultAsmParser : AsmParser;
//
class AsmParserVariant {
// Variant - AsmParsers can be of multiple
diff erent variants. Variants are
- // used to support targets that need to parser multiple formats for the
+ // used to support targets that need to parse multiple formats for the
// assembly language.
int Variant = 0;
@@ -1384,7 +1384,7 @@ def all_of;
/// AssemblerPredicate - This is a Predicate that can be used when the assembler
/// matches instructions and aliases.
class AssemblerPredicate<dag cond, string name = ""> {
- bit AssemblerMatcherPredicate = 1;
+ bit AssemblerMatcherPredicate = true;
dag AssemblerCondDag = cond;
string PredicateName = name;
}
@@ -1459,7 +1459,7 @@ class InstAlias<string Asm, dag Result, int Emit = 1, string VariantName = ""> {
// Setting this to 0 will cause the alias to ignore the Result instruction's
// defined AsmMatchConverter and instead use the function generated by the
// dag Result.
- bit UseInstAsmMatchConverter = 1;
+ bit UseInstAsmMatchConverter = true;
// Assembler variant name to use for this alias. If not specified then
// assembler variants will be determined based on AsmString
diff --git a/llvm/include/llvm/Target/TargetCallingConv.td b/llvm/include/llvm/Target/TargetCallingConv.td
index 057f33083e08..b3d4fe9d0dbb 100644
--- a/llvm/include/llvm/Target/TargetCallingConv.td
+++ b/llvm/include/llvm/Target/TargetCallingConv.td
@@ -187,15 +187,15 @@ class CallingConv<list<CCAction> actions> {
/// If true, this calling convention will be emitted as externally visible in
/// the llvm namespaces instead of as a static function.
- bit Entry = 0;
+ bit Entry = false;
- bit Custom = 0;
+ bit Custom = false;
}
/// CustomCallingConv - An instance of this is used to declare calling
/// conventions that are implemented using a custom function of the same name.
class CustomCallingConv : CallingConv<[]> {
- let Custom = 1;
+ let Custom = true;
}
/// CalleeSavedRegs - A list of callee saved registers for a given calling
diff --git a/llvm/include/llvm/Target/TargetInstrPredicate.td b/llvm/include/llvm/Target/TargetInstrPredicate.td
index 5c5619eb645d..9f2cde9d9230 100644
--- a/llvm/include/llvm/Target/TargetInstrPredicate.td
+++ b/llvm/include/llvm/Target/TargetInstrPredicate.td
@@ -11,7 +11,7 @@
// MCInstPredicate definitions are used by target scheduling models to describe
// constraints on instructions.
//
-// Here is an example of an MCInstPredicate definition in tablegen:
+// Here is an example of an MCInstPredicate definition in TableGen:
//
// def MCInstPredicateExample : CheckAll<[
// CheckOpcode<[BLR]>,
@@ -319,8 +319,8 @@ class DepBreakingClass<list<Instruction> opcodes, MCInstPredicate pred,
// - A list of subtarget hooks (Delegates) that are called from this function.
//
class STIPredicateDecl<string name, MCInstPredicate default = FalsePred,
- bit overrides = 1, bit expandForMC = 1,
- bit updatesOpcodeMask = 0,
+ bit overrides = true, bit expandForMC = true,
+ bit updatesOpcodeMask = false,
list<STIPredicateDecl> delegates = []> {
string Name = name;
@@ -355,7 +355,7 @@ class STIPredicate<STIPredicateDecl declaration,
// Convenience classes and definitions used by processor scheduling models to
// describe dependency breaking instructions and move elimination candidates.
-let UpdatesOpcodeMask = 1 in {
+let UpdatesOpcodeMask = true in {
def IsZeroIdiomDecl : STIPredicateDecl<"isZeroIdiom">;
diff --git a/llvm/include/llvm/Target/TargetItinerary.td b/llvm/include/llvm/Target/TargetItinerary.td
index d364fab038b5..a432d4e42b61 100644
--- a/llvm/include/llvm/Target/TargetItinerary.td
+++ b/llvm/include/llvm/Target/TargetItinerary.td
@@ -8,7 +8,7 @@
//
// This file defines the target-independent scheduling interfaces
// which should be implemented by each target that uses instruction
-// itineraries for scheduling. Itineraries are details reservation
+// itineraries for scheduling. Itineraries are detailed reservation
// tables for each instruction class. They are most appropriate for
// in-order machine with complicated scheduling or bundling constraints.
//
diff --git a/llvm/include/llvm/Target/TargetPfmCounters.td b/llvm/include/llvm/Target/TargetPfmCounters.td
index e1d5013c1291..b00f3e19c35f 100644
--- a/llvm/include/llvm/Target/TargetPfmCounters.td
+++ b/llvm/include/llvm/Target/TargetPfmCounters.td
@@ -7,6 +7,8 @@
//===----------------------------------------------------------------------===//
//
// This file defines the target-independent interfaces for performance counters.
+//
+//===----------------------------------------------------------------------===//
// Definition of a hardware counters from libpfm identifiers.
class PfmCounter<string counter> {
diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td
index 9f2f27ddcb25..a822878ead7f 100644
--- a/llvm/include/llvm/Target/TargetSchedule.td
+++ b/llvm/include/llvm/Target/TargetSchedule.td
@@ -87,7 +87,7 @@ class SchedMachineModel {
// Per-cycle resources tables.
ProcessorItineraries Itineraries = NoItineraries;
- bit PostRAScheduler = 0; // Enable Post RegAlloc Scheduler pass.
+ bit PostRAScheduler = false; // Enable Post RegAlloc Scheduler pass.
// Subtargets that define a model for only a subset of instructions
// that have a scheduling class (itinerary class or SchedRW list)
@@ -96,13 +96,13 @@ class SchedMachineModel {
// be an error. This should only be set during initial bringup,
// or there will be no way to catch simple errors in the model
// resulting from changes to the instruction definitions.
- bit CompleteModel = 1;
+ bit CompleteModel = true;
// Indicates that we should do full overlap checking for multiple InstrRWs
// defining the same instructions within the same SchedMachineModel.
// FIXME: Remove when all in tree targets are clean with the full check
// enabled.
- bit FullInstRWOverlapCheck = 1;
+ bit FullInstRWOverlapCheck = true;
// A processor may only implement part of published ISA, due to either new ISA
// extensions, (e.g. Pentium 4 doesn't have AVX) or implementation
@@ -118,12 +118,12 @@ class SchedMachineModel {
// field.
list<Predicate> UnsupportedFeatures = [];
- bit NoModel = 0; // Special tag to indicate missing machine model.
+ bit NoModel = false; // Special tag to indicate missing machine model.
}
def NoSchedModel : SchedMachineModel {
- let NoModel = 1;
- let CompleteModel = 0;
+ let NoModel = true;
+ let CompleteModel = false;
}
// Define a kind of processor resource that may be common across
@@ -254,14 +254,14 @@ class ProcWriteResources<list<ProcResourceKind> resources> {
list<int> ResourceCycles = [];
int Latency = 1;
int NumMicroOps = 1;
- bit BeginGroup = 0;
- bit EndGroup = 0;
+ bit BeginGroup = false;
+ bit EndGroup = false;
// Allow a processor to mark some scheduling classes as unsupported
// for stronger verification.
- bit Unsupported = 0;
+ bit Unsupported = false;
// Allow a processor to mark some scheduling classes as single-issue.
// SingleIssue is an alias for Begin/End Group.
- bit SingleIssue = 0;
+ bit SingleIssue = false;
SchedMachineModel SchedModel = ?;
}
@@ -317,7 +317,7 @@ class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> {
list<SchedWrite> ValidWrites = writes;
// Allow a processor to mark some scheduling classes as unsupported
// for stronger verification.
- bit Unsupported = 0;
+ bit Unsupported = false;
SchedMachineModel SchedModel = ?;
}
@@ -395,7 +395,7 @@ class SchedVar<SchedPredicateBase pred, list<SchedReadWrite> selected> {
// SchedModel silences warnings but is ignored.
class SchedVariant<list<SchedVar> variants> {
list<SchedVar> Variants = variants;
- bit Variadic = 0;
+ bit Variadic = false;
SchedMachineModel SchedModel = ?;
}
@@ -428,7 +428,7 @@ class InstRW<list<SchedReadWrite> rw, dag instrlist> {
dag Instrs = instrlist;
SchedMachineModel SchedModel = ?;
// Allow a subtarget to mark some instructions as unsupported.
- bit Unsupported = 0;
+ bit Unsupported = false;
}
// Map a set of itinerary classes to SchedReadWrite resources. This is
@@ -535,7 +535,7 @@ class SchedAlias<SchedReadWrite match, SchedReadWrite alias> {
class RegisterFile<int numPhysRegs, list<RegisterClass> Classes = [],
list<int> Costs = [], list<bit> AllowMoveElim = [],
- int MaxMoveElimPerCy = 0, bit AllowZeroMoveElimOnly = 0> {
+ int MaxMoveElimPerCy = 0, bit AllowZeroMoveElimOnly = false> {
list<RegisterClass> RegClasses = Classes;
list<int> RegCosts = Costs;
list<bit> AllowMoveElimination = AllowMoveElim;
diff --git a/llvm/include/llvm/Target/TargetSelectionDAG.td b/llvm/include/llvm/Target/TargetSelectionDAG.td
index d58f7e51509e..20a51cea35ec 100644
--- a/llvm/include/llvm/Target/TargetSelectionDAG.td
+++ b/llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -754,7 +754,7 @@ class PatFrags<dag ops, list<dag> frags, code pred = [{}],
// This is useful when Fragments involves associative / commutative
// operators: a single piece of code can easily refer to all operands even
// when re-associated / commuted variants of the fragment are matched.
- bit PredicateCodeUsesOperands = 0;
+ bit PredicateCodeUsesOperands = false;
// Define a few pre-packaged predicates. This helps GlobalISel import
// existing rules from SelectionDAG for many common cases.
@@ -853,13 +853,13 @@ class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm,
SDNode ImmNode = imm>
: PatFrag<(ops), (vt ImmNode), [{}], xform> {
let ImmediateCode = pred;
- bit FastIselShouldIgnore = 0;
+ bit FastIselShouldIgnore = false;
// Is the data type of the immediate an APInt?
- bit IsAPInt = 0;
+ bit IsAPInt = false;
// Is the data type of the immediate an APFloat?
- bit IsAPFloat = 0;
+ bit IsAPFloat = false;
}
// Convenience wrapper for ImmLeaf to use timm/TargetConstant instead
@@ -876,8 +876,8 @@ class TImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm,
// IntImmLeaf will allow GlobalISel to import the rule.
class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
: ImmLeaf<vt, pred, xform> {
- let IsAPInt = 1;
- let FastIselShouldIgnore = 1;
+ let IsAPInt = true;
+ let FastIselShouldIgnore = true;
}
// An ImmLeaf except that Imm is an APFloat.
@@ -886,8 +886,8 @@ class IntImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
// generate code for rules that make use of it.
class FPImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
: ImmLeaf<vt, pred, xform, fpimm> {
- let IsAPFloat = 1;
- let FastIselShouldIgnore = 1;
+ let IsAPFloat = true;
+ let FastIselShouldIgnore = true;
}
// Leaf fragments.
@@ -915,222 +915,222 @@ def null_frag : SDPatternOperator;
// load fragments.
def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr)> {
- let IsLoad = 1;
- let IsUnindexed = 1;
+ let IsLoad = true;
+ let IsUnindexed = true;
}
def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
- let IsLoad = 1;
- let IsNonExtLoad = 1;
+ let IsLoad = true;
+ let IsNonExtLoad = true;
}
// extending load fragments.
def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
- let IsLoad = 1;
- let IsAnyExtLoad = 1;
+ let IsLoad = true;
+ let IsAnyExtLoad = true;
}
def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
- let IsLoad = 1;
- let IsSignExtLoad = 1;
+ let IsLoad = true;
+ let IsSignExtLoad = true;
}
def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr)> {
- let IsLoad = 1;
- let IsZeroExtLoad = 1;
+ let IsLoad = true;
+ let IsZeroExtLoad = true;
}
def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i1;
}
def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i8;
}
def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i16;
}
def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i32;
}
def extloadf16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = f16;
}
def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = f32;
}
def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = f64;
}
def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i1;
}
def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i8;
}
def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i16;
}
def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i32;
}
def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i1;
}
def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i8;
}
def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i16;
}
def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let MemoryVT = i32;
}
def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i1;
}
def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i8;
}
def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i16;
}
def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i32;
}
def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = f32;
}
def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = f64;
}
def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i1;
}
def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i8;
}
def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i16;
}
def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i32;
}
def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i1;
}
def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i8;
}
def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i16;
}
def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr)> {
- let IsLoad = 1;
+ let IsLoad = true;
let ScalarMemoryVT = i32;
}
// store fragments.
def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
(st node:$val, node:$ptr)> {
- let IsStore = 1;
- let IsUnindexed = 1;
+ let IsStore = true;
+ let IsUnindexed = true;
}
def store : PatFrag<(ops node:$val, node:$ptr),
(unindexedstore node:$val, node:$ptr)> {
- let IsStore = 1;
- let IsTruncStore = 0;
+ let IsStore = true;
+ let IsTruncStore = false;
}
// truncstore fragments.
def truncstore : PatFrag<(ops node:$val, node:$ptr),
(unindexedstore node:$val, node:$ptr)> {
- let IsStore = 1;
- let IsTruncStore = 1;
+ let IsStore = true;
+ let IsTruncStore = true;
}
def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i8;
}
def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i16;
}
def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i32;
}
def truncstoref16 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = f16;
}
def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = f32;
}
def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = f64;
}
def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
- let IsStore = 1;
+ let IsStore = true;
let ScalarMemoryVT = i8;
}
def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
- let IsStore = 1;
+ let IsStore = true;
let ScalarMemoryVT = i16;
}
def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr),
(truncstore node:$val, node:$ptr)> {
- let IsStore = 1;
+ let IsStore = true;
let ScalarMemoryVT = i32;
}
// indexed store fragments.
def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
- let IsTruncStore = 0;
+ let IsStore = true;
+ let IsTruncStore = false;
}
def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
@@ -1141,8 +1141,8 @@ def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
(ist node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
- let IsTruncStore = 1;
+ let IsStore = true;
+ let IsTruncStore = true;
}
def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
(itruncstore node:$val, node:$base, node:$offset), [{
@@ -1151,37 +1151,37 @@ def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
}]>;
def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i1;
}
def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i8;
}
def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i16;
}
def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i32;
}
def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = f32;
}
def pre_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let ScalarMemoryVT = i8;
}
def pre_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(pre_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let ScalarMemoryVT = i16;
}
@@ -1198,37 +1198,37 @@ def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
}]>;
def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i1;
}
def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i8;
}
def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i16;
}
def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = i32;
}
def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let MemoryVT = f32;
}
def post_truncstvi8 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let ScalarMemoryVT = i8;
}
def post_truncstvi16 : PatFrag<(ops node:$val, node:$base, node:$offset),
(post_truncst node:$val, node:$base, node:$offset)> {
- let IsStore = 1;
+ let IsStore = true;
let ScalarMemoryVT = i16;
}
@@ -1435,78 +1435,78 @@ def any_fsetccs : PatFrags<(ops node:$lhs, node:$rhs, node:$pred),
multiclass binary_atomic_op_ord<SDNode atomic_op> {
def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingMonotonic = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingMonotonic = true;
}
def NAME#_acquire : PatFrag<(ops node:$ptr, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingAcquire = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingAcquire = true;
}
def NAME#_release : PatFrag<(ops node:$ptr, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingRelease = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingRelease = true;
}
def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingAcquireRelease = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingAcquireRelease = true;
}
def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingSequentiallyConsistent = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingSequentiallyConsistent = true;
}
}
multiclass ternary_atomic_op_ord<SDNode atomic_op> {
def NAME#_monotonic : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingMonotonic = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingMonotonic = true;
}
def NAME#_acquire : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingAcquire = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingAcquire = true;
}
def NAME#_release : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingRelease = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingRelease = true;
}
def NAME#_acq_rel : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingAcquireRelease = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingAcquireRelease = true;
}
def NAME#_seq_cst : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
(!cast<SDPatternOperator>(NAME) node:$ptr, node:$cmp, node:$val)> {
- let IsAtomic = 1;
- let IsAtomicOrderingSequentiallyConsistent = 1;
+ let IsAtomic = true;
+ let IsAtomicOrderingSequentiallyConsistent = true;
}
}
multiclass binary_atomic_op<SDNode atomic_op, bit IsInt = 1> {
def _8 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = !if(IsInt, i8, ?);
}
def _16 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = !if(IsInt, i16, f16);
}
def _32 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = !if(IsInt, i32, f32);
}
def _64 : PatFrag<(ops node:$ptr, node:$val),
(atomic_op node:$ptr, node:$val)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = !if(IsInt, i64, f64);
}
@@ -1519,22 +1519,22 @@ multiclass binary_atomic_op<SDNode atomic_op, bit IsInt = 1> {
multiclass ternary_atomic_op<SDNode atomic_op> {
def _8 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
(atomic_op node:$ptr, node:$cmp, node:$val)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = i8;
}
def _16 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
(atomic_op node:$ptr, node:$cmp, node:$val)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = i16;
}
def _32 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
(atomic_op node:$ptr, node:$cmp, node:$val)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = i32;
}
def _64 : PatFrag<(ops node:$ptr, node:$cmp, node:$val),
(atomic_op node:$ptr, node:$cmp, node:$val)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = i64;
}
@@ -1562,25 +1562,25 @@ defm atomic_cmp_swap : ternary_atomic_op<atomic_cmp_swap>;
def atomic_load_8 :
PatFrag<(ops node:$ptr),
(atomic_load node:$ptr)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = i8;
}
def atomic_load_16 :
PatFrag<(ops node:$ptr),
(atomic_load node:$ptr)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = i16;
}
def atomic_load_32 :
PatFrag<(ops node:$ptr),
(atomic_load node:$ptr)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = i32;
}
def atomic_load_64 :
PatFrag<(ops node:$ptr),
(atomic_load node:$ptr)> {
- let IsAtomic = 1;
+ let IsAtomic = true;
let MemoryVT = i64;
}
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