[PATCH] D86519: [SystemZ] New pass for domain reassignment from integer to vector.
Jonas Paulsson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 17 04:51:53 PST 2020
jonpa updated this revision to Diff 305744.
jonpa added a comment.
Patch still experimental, but updated with latest changes.
Instead of making a closure illegal at the point of an impossible conversion, keep sets of Insertions and Extractions and allow more cases of inserting and extracting registers. In particular, if a reassigned register is defined inside a loop, an extraction is allowed (only) if the scalar instruction is outside of the loop.
findExtractionInsPt() determines if a closure with needed extraction is legal, and if so where to place the extraction.
Legal closures found: 1450688 (7x from last week)
Reassigned closures: 21415 (+30% from last week, but still very little)
Closures not possible to reassign at point of query: 225077
Due to
Extraction not allowed unless outside of loop: 221314
- COPY (to physreg) : 25572
Crossing a call : 62587
The picture in the debug dump is now very different since a lot of closures now depend on an extraction of the result..
It seems that it could be worth trying to do more extractions - for instance also if a defining instruction is before the loop and not just for those inside of it...
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D86519/new/
https://reviews.llvm.org/D86519
Files:
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/SystemZ/CMakeLists.txt
llvm/lib/Target/SystemZ/SystemZ.h
llvm/lib/Target/SystemZ/SystemZDomainReassignment.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.h
llvm/lib/Target/SystemZ/SystemZInstrVector.td
llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
llvm/test/CodeGen/SystemZ/buildvector-00.ll
llvm/test/CodeGen/SystemZ/dag-combine-01.ll
llvm/test/CodeGen/SystemZ/dag-combine-03.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-01.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-02.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-03.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-04.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-05.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-06.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-07.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-08.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-09.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-10.mir
llvm/test/CodeGen/SystemZ/domain-reassignment-11.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-12.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-13.ll
llvm/test/CodeGen/SystemZ/domain-reassignment-14.ll
llvm/test/CodeGen/SystemZ/knownbits.ll
llvm/test/CodeGen/SystemZ/stack-clash-protection.ll
llvm/test/CodeGen/SystemZ/subregliveness-04.ll
llvm/test/CodeGen/SystemZ/tls-08.ll
llvm/test/CodeGen/SystemZ/vec-trunc-to-i1.ll
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