[PATCH] D91589: [DAGCombiner] Fold (sext (not i1 x)) -> (add (zext i1 x), -1)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Maybe add RISCV tests? That's another target that stores compare results as 0/1 instead of 0/-1 - could you also pre-commit the tests for RISCV/SystemZ with current codegen and rebase the patch to show the diff?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D91589/new/

https://reviews.llvm.org/D91589