[PATCH] D91512: [AArch64][Isel] Avoid implicit zext for SIGN_EXTEND_INREG ( TRUNCATE )

Tim Northover via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 17 01:53:39 PST 2020


t.p.northover added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.h:436
+
+  if (Opc == ISD::SIGN_EXTEND_INREG) {
+    SDValue Opr = N.getOperand(0);
----------------
Could we fix `isBitfieldExtractOpFromSExtInReg` to produce `SBFMWri` instead?

The other cases here seem to be nodes that we'd have to pessimize in the general case to ensure they zero the high bits on the off-chance they're needed, but for sign-extension it's just a quirk of the implementation.


================
Comment at: llvm/test/CodeGen/AArch64/aarch64-avoid-implicit-zext-for-SIGN_EXTEND_INREG.ll:2
+; RUN: llc -O3 -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
+ at b = dso_local local_unnamed_addr global { [3 x i8], i8, i8, i8, i8, i8 } { [3 x i8] undef, i8 -64, i8 74, i8 -9, i8 -1, i8 7 }, align 8
+ at c = common dso_local local_unnamed_addr global i64 0, align 8
----------------
Could you try to simplify this a bit more? There are lots of stray annotations, both calls appear to be unnecessary, and as far as I can tell `%bf.load` could just as easily be a function argument.


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  https://reviews.llvm.org/D91512/new/

https://reviews.llvm.org/D91512



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