[PATCH] D90738: [RISCV] Support Zfh half-precision floating-point extension.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:992
 
+static Register convertFPR64ToFPR16(Register Reg) {
+  assert(Reg >= RISCV::F0_D && Reg <= RISCV::F31_D && "Invalid register");
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This needs to be rebased. This file uses MCRegister instead of Register now.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2738
     return "RISCVISD::FMV_X_ANYEXTW_RV64";
+  case RISCVISD::FMV_H_X_RV32:
+    return "RISCVISD::FMV_H_X_RV32";
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This needs to be rebased to use NODE_NAME_CASE macros.


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Comment at: llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll:110
+; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
+; operations if halfing point isn't supported. A combine could be written to
+; do the same even when f16 is legal.
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"halfing point" here looks like a bad search and replace of "float". Can you change to "half precision floating point" and check if this occurs anywhere else.


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Comment at: llvm/test/CodeGen/RISCV/half-convert.ll:475
+; RV64IF-LP64F-NEXT:    ret
+  %1 = fptrunc double %a to half
+  ret half %1
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Are we missing coverage of conversions to/from double with D extension enabled?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90738/new/

https://reviews.llvm.org/D90738