[PATCH] D91561: [MachineScheduler] Inform pass infra of post-ra scheduler's dependencies
Jon Roelofs via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 16 12:36:07 PST 2020
jroelofs created this revision.
jroelofs added reviewers: dmgreen, hfinkel.
Herald added subscribers: llvm-commits, ecnelises, javed.absar, hiraditya, MatzeB.
Herald added a project: LLVM.
jroelofs requested review of this revision.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D91561
Files:
llvm/lib/CodeGen/MachineScheduler.cpp
Index: llvm/lib/CodeGen/MachineScheduler.cpp
===================================================================
--- llvm/lib/CodeGen/MachineScheduler.cpp
+++ llvm/lib/CodeGen/MachineScheduler.cpp
@@ -240,8 +240,13 @@
char &llvm::PostMachineSchedulerID = PostMachineScheduler::ID;
-INITIALIZE_PASS(PostMachineScheduler, "postmisched",
- "PostRA Machine Instruction Scheduler", false, false)
+INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched",
+ "PostRA Machine Instruction Scheduler", false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
+INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
+INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
+INITIALIZE_PASS_END(PostMachineScheduler, "postmisched",
+ "PostRA Machine Instruction Scheduler", false, false)
PostMachineScheduler::PostMachineScheduler() : MachineSchedulerBase(ID) {
initializePostMachineSchedulerPass(*PassRegistry::getPassRegistry());
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