[PATCH] D88485: [SDag][AMDGPU] Maintain DAG divergence through instruction selection

[Alexander via Phabricator via llvm-commits]

alex-t added a comment.

It is not clear to me why do we need to query divergence information for MachineSDNode? 
After unstruction selection is done we should have all the instructions selected correctly to VALU vs SALU basing on the information that is available at the selection stage.
Thus, we can use isDivergent bit value set for the MachineSDNode in case we need to recompute or update divergence information after selection.
So, instead of adding machine opcodes to isSDNodeSourceOfDivergence it is better to mark that opcodes right away as they are selected.

After the selection is done we'd rather interested in VALU or SALU property instead of divergence. We have lots of opcodes that are VALU even if uniform.
For that we may like to have theseparate analysis pass that could work similar to the divergence analysis but propagate the VALU/SALU property instead of divergence.
BUt creating such a "one more divergence analysis" upon the MIR requires a lot of efforts and strong reasons.


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https://reviews.llvm.org/D88485