[PATCH] D91529: [llvm-readobj] [ARMWinEH] Clearly print an invalid case of packed unwind info as such

Martin Storsjö via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Nov 16 03:55:30 PST 2020


mstorsjo created this revision.
mstorsjo added reviewers: efriedma, TomTan.
Herald added subscribers: rupprecht, kristof.beyls.
Herald added a reviewer: jhenderson.
Herald added a project: LLVM.
mstorsjo requested review of this revision.
Herald added a subscriber: MaskRay.

As the actual windows unwinder doesn't support this case, don't pretend that it is supported when dumping the generated unwind info either, even if it would be possible to interpret it as something sensible.

This should reduce the risk of us emitting such a case in code (although it's unlikely as long as the unwind info is generated through the SEH opcodes, as the opcodes can't describe this case).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91529

Files:
  llvm/test/tools/llvm-readobj/COFF/arm64-packed-unwind.s
  llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp


Index: llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
===================================================================
--- llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
+++ llvm/tools/llvm-readobj/ARMWinEHPrinter.cpp
@@ -1223,10 +1223,12 @@
     if (I == (RF.RegI() + 1) / 2 - 1 && RF.RegI() % 2 == 1) {
       // The last register, an odd register without a pair
       if (RF.CR() == 1) {
-        if (I == 0) // If this is the only register pair
-          SW.startLine() << format("stp x%d, lr, [sp, #-%d]!\n", 19 + 2 * I,
-                                   SavSZ);
-        else
+        if (I == 0) { // If this is the only register pair
+          // CR=1 combined with RegI=1 doesn't map to a documented case;
+          // it doesn't map to any regular unwind info opcode, and the
+          // actual unwinder doesn't support it.
+          SW.startLine() << "INVALID!\n";
+        } else
           SW.startLine() << format("stp x%d, lr, [sp, #%d]\n", 19 + 2 * I,
                                    16 * I);
       } else {
Index: llvm/test/tools/llvm-readobj/COFF/arm64-packed-unwind.s
===================================================================
--- llvm/test/tools/llvm-readobj/COFF/arm64-packed-unwind.s
+++ llvm/test/tools/llvm-readobj/COFF/arm64-packed-unwind.s
@@ -139,7 +139,7 @@
 // CHECK-NEXT:     FrameSize: 32
 // CHECK-NEXT:     Prologue [
 // CHECK-NEXT:       sub sp, sp, #16
-// CHECK-NEXT:       stp x19, lr, [sp, #-16]!
+// CHECK-NEXT:       INVALID!
 // CHECK-NEXT:       end
 // CHECK-NEXT:     ]
 // CHECK-NEXT:   }


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