[llvm] e0c92c6 - [VE] Add pfchv intrinsic instructions

[Kazushi Marukawa via llvm-commits]

Author: Kazushi (Jam) Marukawa
Date: 2020-11-16T20:10:44+09:00
New Revision: e0c92c6c03772ca97285367bb460dafa58beb0c0

URL: https://github.com/llvm/llvm-project/commit/e0c92c6c03772ca97285367bb460dafa58beb0c0
DIFF: https://github.com/llvm/llvm-project/commit/e0c92c6c03772ca97285367bb460dafa58beb0c0.diff

LOG: [VE] Add pfchv intrinsic instructions

Add pfchv intrinsic instructions and a regression test.

Reviewed By: simoll

Differential Revision: https://reviews.llvm.org/D91522

Added: 
    llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll

Modified: 
    llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
    llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td

Removed: 
    


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diff  --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
index 86179358f109..56d0226181df 100644
--- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
+++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
@@ -78,3 +78,5 @@ let TargetPrefix = "ve" in def int_ve_vl_vstl2dot_vssl : GCCBuiltin<"__builtin_v
 let TargetPrefix = "ve" in def int_ve_vl_vstl2dot_vssml : GCCBuiltin<"__builtin_ve_vl_vstl2dot_vssml">, Intrinsic<[], [LLVMType<v256f64>, LLVMType<i64>, llvm_ptr_ty, LLVMType<v256i1>, LLVMType<i32>], [IntrWriteMem]>;
 let TargetPrefix = "ve" in def int_ve_vl_vstl2dncot_vssl : GCCBuiltin<"__builtin_ve_vl_vstl2dncot_vssl">, Intrinsic<[], [LLVMType<v256f64>, LLVMType<i64>, llvm_ptr_ty, LLVMType<i32>], [IntrWriteMem]>;
 let TargetPrefix = "ve" in def int_ve_vl_vstl2dncot_vssml : GCCBuiltin<"__builtin_ve_vl_vstl2dncot_vssml">, Intrinsic<[], [LLVMType<v256f64>, LLVMType<i64>, llvm_ptr_ty, LLVMType<v256i1>, LLVMType<i32>], [IntrWriteMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pfchv_ssl : GCCBuiltin<"__builtin_ve_vl_pfchv_ssl">, Intrinsic<[], [LLVMType<i64>, llvm_ptr_ty, LLVMType<i32>], [IntrInaccessibleMemOrArgMemOnly]>;
+let TargetPrefix = "ve" in def int_ve_vl_pfchvnc_ssl : GCCBuiltin<"__builtin_ve_vl_pfchvnc_ssl">, Intrinsic<[], [LLVMType<i64>, llvm_ptr_ty, LLVMType<i32>], [IntrInaccessibleMemOrArgMemOnly]>;

diff  --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
index 6ff9f9c4cb7d..175215532cc6 100644
--- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
+++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
@@ -158,3 +158,7 @@ def : Pat<(int_ve_vl_vstl2dncot_vssl v256f64:$vx, i64:$sy, i64:$sz, i32:$vl), (V
 def : Pat<(int_ve_vl_vstl2dncot_vssl v256f64:$vx, simm7:$I, i64:$sz, i32:$vl), (VSTL2DNCOTirvl (LO7 $I), i64:$sz, v256f64:$vx, i32:$vl)>;
 def : Pat<(int_ve_vl_vstl2dncot_vssml v256f64:$vx, i64:$sy, i64:$sz, v256i1:$vm, i32:$vl), (VSTL2DNCOTrrvml i64:$sy, i64:$sz, v256f64:$vx, v256i1:$vm, i32:$vl)>;
 def : Pat<(int_ve_vl_vstl2dncot_vssml v256f64:$vx, simm7:$I, i64:$sz, v256i1:$vm, i32:$vl), (VSTL2DNCOTirvml (LO7 $I), i64:$sz, v256f64:$vx, v256i1:$vm, i32:$vl)>;
+def : Pat<(int_ve_vl_pfchv_ssl i64:$sy, i64:$sz, i32:$vl), (PFCHVrrl i64:$sy, i64:$sz, i32:$vl)>;
+def : Pat<(int_ve_vl_pfchv_ssl simm7:$I, i64:$sz, i32:$vl), (PFCHVirl (LO7 $I), i64:$sz, i32:$vl)>;
+def : Pat<(int_ve_vl_pfchvnc_ssl i64:$sy, i64:$sz, i32:$vl), (PFCHVNCrrl i64:$sy, i64:$sz, i32:$vl)>;
+def : Pat<(int_ve_vl_pfchvnc_ssl simm7:$I, i64:$sz, i32:$vl), (PFCHVNCirl (LO7 $I), i64:$sz, i32:$vl)>;

diff  --git a/llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll b/llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll
new file mode 100644
index 000000000000..298b6909aa59
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/pfchv.ll
@@ -0,0 +1,60 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test prefetch vector intrinsic instructions
+;;;
+;;; Note:
+;;;   We test PFCHVrrl, PFCHVirl, PFCHVNCrrl, and PFCHVNCirl instructions.
+
+; Function Attrs: nounwind
+define void @pfchv_vssl(i8* %0, i64 %1) {
+; CHECK-LABEL: pfchv_vssl:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
+; CHECK-NEXT:    pfchv %s1, %s0
+; CHECK-NEXT:    or %s11, 0, %s9
+  tail call void @llvm.ve.vl.pfchv.ssl(i64 %1, i8* %0, i32 256)
+  ret void
+}
+
+; Function Attrs: inaccessiblemem_or_argmemonly nounwind
+declare void @llvm.ve.vl.pfchv.ssl(i64, i8*, i32)
+
+; Function Attrs: nounwind
+define void @pfchv_vssl_imm(i8* %0) {
+; CHECK-LABEL: pfchv_vssl_imm:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    pfchv 8, %s0
+; CHECK-NEXT:    or %s11, 0, %s9
+  tail call void @llvm.ve.vl.pfchv.ssl(i64 8, i8* %0, i32 256)
+  ret void
+}
+
+; Function Attrs: nounwind
+define void @pfchvnc_vssl(i8* %0, i64 %1) {
+; CHECK-LABEL: pfchvnc_vssl:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s2, 256
+; CHECK-NEXT:    lvl %s2
+; CHECK-NEXT:    pfchv.nc %s1, %s0
+; CHECK-NEXT:    or %s11, 0, %s9
+  tail call void @llvm.ve.vl.pfchvnc.ssl(i64 %1, i8* %0, i32 256)
+  ret void
+}
+
+; Function Attrs: inaccessiblemem_or_argmemonly nounwind
+declare void @llvm.ve.vl.pfchvnc.ssl(i64, i8*, i32)
+
+; Function Attrs: nounwind
+define void @pfchvnc_vssl_imm(i8* %0) {
+; CHECK-LABEL: pfchvnc_vssl_imm:
+; CHECK:       .LBB{{[0-9]+}}_2:
+; CHECK-NEXT:    lea %s1, 256
+; CHECK-NEXT:    lvl %s1
+; CHECK-NEXT:    pfchv.nc 8, %s0
+; CHECK-NEXT:    or %s11, 0, %s9
+  tail call void @llvm.ve.vl.pfchvnc.ssl(i64 8, i8* %0, i32 256)
+  ret void
+}