[llvm] 48b43c9 - [ARM] Cortex-M7 schedule
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 16 02:16:21 PST 2020
Author: David Penry
Date: 2020-11-16T10:16:07Z
New Revision: 48b43c9d4f038a85cb08601922cb362c169d57e3
URL: https://github.com/llvm/llvm-project/commit/48b43c9d4f038a85cb08601922cb362c169d57e3
DIFF: https://github.com/llvm/llvm-project/commit/48b43c9d4f038a85cb08601922cb362c169d57e3.diff
LOG: [ARM] Cortex-M7 schedule
This patch adds the SchedMachineModel for Cortex-M7. It
also adds test cases for the scheduling information.
Details of the pipeline and descriptions are in comments
in file ARMScheduleM7.td included in this patch.
Differential Revision: https://reviews.llvm.org/D91355
Added:
llvm/lib/Target/ARM/ARMScheduleM7.td
llvm/test/tools/llvm-mca/ARM/m7-fp.s
llvm/test/tools/llvm-mca/ARM/m7-int.s
Modified:
llvm/lib/Target/ARM/ARM.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td
index fac6fea35f3e..94e147b29920 100644
--- a/llvm/lib/Target/ARM/ARM.td
+++ b/llvm/lib/Target/ARM/ARM.td
@@ -918,6 +918,7 @@ include "ARMScheduleSwift.td"
include "ARMScheduleR52.td"
include "ARMScheduleA57.td"
include "ARMScheduleM4.td"
+include "ARMScheduleM7.td"
//===----------------------------------------------------------------------===//
// ARM processors
@@ -1159,8 +1160,9 @@ def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em,
FeatureUseMISched,
FeatureHasNoBranchPredictor]>;
-def : ProcNoItin<"cortex-m7", [ARMv7em,
- FeatureFPARMv8_D16]>;
+def : ProcessorModel<"cortex-m7", CortexM7Model, [ARMv7em,
+ FeatureFPARMv8_D16,
+ FeatureUseMISched]>;
def : ProcNoItin<"cortex-m23", [ARMv8mBaseline,
FeatureNoMovt]>;
diff --git a/llvm/lib/Target/ARM/ARMScheduleM7.td b/llvm/lib/Target/ARM/ARMScheduleM7.td
new file mode 100644
index 000000000000..12296ad09218
--- /dev/null
+++ b/llvm/lib/Target/ARM/ARMScheduleM7.td
@@ -0,0 +1,488 @@
+//=- ARMScheduleM7.td - ARM Cortex-M7 Scheduling Definitions -*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the SchedRead/Write data for the ARM Cortex-M7 processor.
+//
+//===----------------------------------------------------------------------===//
+
+def CortexM7Model : SchedMachineModel {
+ let IssueWidth = 2; // Dual issue for most instructions.
+ let MicroOpBufferSize = 0; // The Cortex-M7 is in-order.
+ let LoadLatency = 2; // Best case for load-use case.
+ let MispredictPenalty = 4; // Mispredict cost for forward branches is 6,
+ // but 4 works better
+ let CompleteModel = 0;
+}
+
+//===--------------------------------------------------------------------===//
+// The Cortex-M7 has two ALU, two LOAD, a STORE, a MAC, a BRANCH and a VFP
+// pipe. The stages relevant to scheduling are as follows:
+//
+// EX1: address generation shifts
+// EX2: fast load data ALUs FP operation
+// EX3: slow load data integer writeback FP operation
+// EX4: store data FP writeback
+//
+// There are shifters in both EX1 and EX2, and some instructions can be
+// flexibly allocated between them. EX2 is used as the "zero" point
+// for scheduling, so simple ALU operations executing in EX2 will have
+// ReadAdvance<0> (the default) for their source operands and Latency = 1.
+
+def M7UnitLoad : ProcResource<2> { let BufferSize = 0; }
+def M7UnitStore : ProcResource<1> { let BufferSize = 0; }
+def M7UnitALU : ProcResource<2>;
+def M7UnitShift1 : ProcResource<1> { let BufferSize = 0; }
+def M7UnitShift2 : ProcResource<1> { let BufferSize = 0; }
+def M7UnitMAC : ProcResource<1> { let BufferSize = 0; }
+def M7UnitBranch : ProcResource<1> { let BufferSize = 0; }
+def M7UnitVFP : ProcResource<1> { let BufferSize = 0; }
+def M7UnitVPort : ProcResource<2> { let BufferSize = 0; }
+def M7UnitSIMD : ProcResource<1> { let BufferSize = 0; }
+
+//===---------------------------------------------------------------------===//
+// Subtarget-specific SchedWrite types with map ProcResources and set latency.
+
+let SchedModel = CortexM7Model in {
+
+def : WriteRes<WriteALU, [M7UnitALU]> { let Latency = 1; }
+
+// Basic ALU with shifts.
+let Latency = 1 in {
+ def : WriteRes<WriteALUsi, [M7UnitALU, M7UnitShift1]>;
+ def : WriteRes<WriteALUsr, [M7UnitALU, M7UnitShift1]>;
+ def : WriteRes<WriteALUSsr, [M7UnitALU, M7UnitShift1]>;
+}
+
+// Compares.
+def : WriteRes<WriteCMP, [M7UnitALU]> { let Latency = 1; }
+def : WriteRes<WriteCMPsi, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
+def : WriteRes<WriteCMPsr, [M7UnitALU, M7UnitShift1]> { let Latency = 2; }
+
+// Multiplies.
+let Latency = 2 in {
+ def : WriteRes<WriteMUL16, [M7UnitMAC]>;
+ def : WriteRes<WriteMUL32, [M7UnitMAC]>;
+ def : WriteRes<WriteMUL64Lo, [M7UnitMAC]>;
+ def : WriteRes<WriteMUL64Hi, []> { let NumMicroOps = 0; }
+}
+
+// Multiply-accumulates.
+let Latency = 2 in {
+ def : WriteRes<WriteMAC16, [M7UnitMAC]>;
+ def : WriteRes<WriteMAC32, [M7UnitMAC]>;
+ def : WriteRes<WriteMAC64Lo, [M7UnitMAC]> { let Latency = 2; }
+ def : WriteRes<WriteMAC64Hi, []> { let NumMicroOps = 0; }
+}
+
+// Divisions.
+// These cannot be dual-issued with any instructions.
+def : WriteRes<WriteDIV, [M7UnitALU]> {
+ let Latency = 7;
+ let SingleIssue = 1;
+}
+
+// Loads/Stores.
+def : WriteRes<WriteLd, [M7UnitLoad]> { let Latency = 1; }
+def : WriteRes<WritePreLd, [M7UnitLoad]> { let Latency = 2; }
+def : WriteRes<WriteST, [M7UnitStore]> { let Latency = 2; }
+
+// Branches.
+def : WriteRes<WriteBr, [M7UnitBranch]> { let Latency = 2; }
+def : WriteRes<WriteBrL, [M7UnitBranch]> { let Latency = 2; }
+def : WriteRes<WriteBrTbl, [M7UnitBranch]> { let Latency = 2; }
+
+// Noop.
+def : WriteRes<WriteNoop, []> { let Latency = 0; }
+
+//===---------------------------------------------------------------------===//
+// Sched definitions for floating-point instructions
+//
+// Floating point conversions.
+def : WriteRes<WriteFPCVT, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
+def : WriteRes<WriteFPMOV, [M7UnitVPort]> { let Latency = 3; }
+
+// The FP pipeline has a latency of 3 cycles.
+// ALU operations (32/64-bit). These go down the FP pipeline.
+def : WriteRes<WriteFPALU32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
+def : WriteRes<WriteFPALU64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
+ let Latency = 4;
+ let BeginGroup = 1;
+}
+
+// Multiplication
+def : WriteRes<WriteFPMUL32, [M7UnitVFP, M7UnitVPort]> { let Latency = 3; }
+def : WriteRes<WriteFPMUL64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
+ let Latency = 7;
+ let BeginGroup = 1;
+}
+
+// Multiply-accumulate. FPMAC goes down the FP Pipeline.
+def : WriteRes<WriteFPMAC32, [M7UnitVFP, M7UnitVPort]> { let Latency = 6; }
+def : WriteRes<WriteFPMAC64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
+ let Latency = 11;
+ let BeginGroup = 1;
+}
+
+// Division. Effective scheduling latency is 3, though real latency is larger
+def : WriteRes<WriteFPDIV32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
+def : WriteRes<WriteFPDIV64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
+ let Latency = 30;
+ let BeginGroup = 1;
+}
+
+// Square-root. Effective scheduling latency is 3; real latency is larger
+def : WriteRes<WriteFPSQRT32, [M7UnitVFP, M7UnitVPort]> { let Latency = 16; }
+def : WriteRes<WriteFPSQRT64, [M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
+ let Latency = 30;
+ let BeginGroup = 1;
+}
+
+def M7WriteShift2 : SchedWriteRes<[M7UnitALU, M7UnitShift2]> {}
+
+// Not used for M7, but needing definitions anyway
+def : WriteRes<WriteVLD1, []>;
+def : WriteRes<WriteVLD2, []>;
+def : WriteRes<WriteVLD3, []>;
+def : WriteRes<WriteVLD4, []>;
+def : WriteRes<WriteVST1, []>;
+def : WriteRes<WriteVST2, []>;
+def : WriteRes<WriteVST3, []>;
+def : WriteRes<WriteVST4, []>;
+
+def M7SingleIssue : SchedWriteRes<[]> {
+ let SingleIssue = 1;
+ let NumMicroOps = 0;
+}
+def M7Slot0Only : SchedWriteRes<[]> {
+ let BeginGroup = 1;
+ let NumMicroOps = 0;
+}
+
+// What pipeline stage operands need to be ready for depending on
+// where they come from.
+def : ReadAdvance<ReadALUsr, 0>;
+def : ReadAdvance<ReadMUL, 0>;
+def : ReadAdvance<ReadMAC, 1>;
+def : ReadAdvance<ReadALU, 0>;
+def : ReadAdvance<ReadFPMUL, 0>;
+def : ReadAdvance<ReadFPMAC, 3>;
+def M7Read_ISS : SchedReadAdvance<-1>; // operands needed at EX1
+def M7Read_EX2 : SchedReadAdvance<1>; // operands needed at EX3
+def M7Read_EX3 : SchedReadAdvance<2>; // operands needed at EX4
+
+// Non general purpose instructions may not be dual issued. These
+// use both issue units.
+def M7NonGeneralPurpose : SchedWriteRes<[]> {
+ // Assume that these will go down the main ALU pipeline.
+ // In reality, many look likely to stall the whole pipeline.
+ let Latency = 3;
+ let SingleIssue = 1;
+}
+
+// List the non general purpose instructions.
+def : InstRW<[M7NonGeneralPurpose], (instregex "t2MRS", "tSVC", "tBKPT",
+ "t2MSR", "t2DMB", "t2DSB", "t2ISB",
+ "t2HVC", "t2SMC", "t2UDF", "ERET",
+ "tHINT", "t2HINT", "t2CLREX", "BUNDLE")>;
+
+//===---------------------------------------------------------------------===//
+// Sched definitions for load/store
+//
+// Mark whether the loads/stores must be single-issue
+// Address operands are needed earlier
+// Data operands are needed later
+
+def M7BaseUpdate : SchedWriteRes<[]> {
+ let Latency = 0; // Update is bypassable out of EX1
+ let NumMicroOps = 0;
+}
+def M7LoadLatency1 : SchedWriteRes<[]> {
+ let Latency = 1;
+ let NumMicroOps = 0;
+}
+def M7SlowLoad : SchedWriteRes<[M7UnitLoad]> { let Latency = 2; }
+
+// Byte and half-word loads should have greater latency than other loads.
+// So should load exclusive.
+
+def : InstRW<[M7SlowLoad],
+ (instregex "t2LDR(B|H|SB|SH)pc")>;
+def : InstRW<[M7SlowLoad, M7Read_ISS],
+ (instregex "t2LDR(B|H|SB|SH)T", "t2LDR(B|H|SB|SH)i",
+ "tLDR(B|H)i")>;
+def : InstRW<[M7SlowLoad, M7Read_ISS, M7Read_ISS],
+ (instregex "t2LDR(B|H|SB|SH)s", "tLDR(B|H)r", "tLDR(SB|SH)")>;
+def : InstRW<[M7SlowLoad, M7BaseUpdate, M7Read_ISS],
+ (instregex "t2LDR(B|H|SB|SH)_(POST|PRE)")>;
+
+// Exclusive loads/stores cannot be dual-issued
+def : InstRW<[WriteLd, M7Slot0Only, M7Read_ISS],
+ (instregex "t2LDREX$")>;
+def : InstRW<[M7SlowLoad, M7Slot0Only, M7Read_ISS],
+ (instregex "t2LDREX(B|H)")>;
+def : InstRW<[WriteST, M7SingleIssue, M7Read_EX2, M7Read_ISS],
+ (instregex "t2STREX(B|H)?$")>;
+
+// Load/store multiples cannot be dual-issued. Note that default scheduling
+// occurs around read/write times of individual registers in the list; read
+// time for STM cannot be overridden because it is a variadic source operand.
+
+def : InstRW<[WriteLd, M7SingleIssue, M7Read_ISS],
+ (instregex "(t|t2)LDM(DB|IA)$")>;
+def : InstRW<[WriteST, M7SingleIssue, M7Read_ISS],
+ (instregex "(t|t2)STM(DB|IA)$")>;
+def : InstRW<[M7BaseUpdate, WriteLd, M7SingleIssue, M7Read_ISS],
+ (instregex "(t|t2)LDM(DB|IA)_UPD$", "tPOP")>;
+def : InstRW<[M7BaseUpdate, WriteST, M7SingleIssue, M7Read_ISS],
+ (instregex "(t|t2)STM(DB|IA)_UPD$", "tPUSH")>;
+
+// Load/store doubles cannot be dual-issued.
+
+def : InstRW<[M7BaseUpdate, WriteST, M7SingleIssue,
+ M7Read_EX2, M7Read_EX2, M7Read_ISS],
+ (instregex "t2STRD_(PRE|POST)")>;
+def : InstRW<[WriteST, M7SingleIssue, M7Read_EX2, M7Read_EX2, M7Read_ISS],
+ (instregex "t2STRDi")>;
+def : InstRW<[WriteLd, M7LoadLatency1, M7SingleIssue, M7BaseUpdate, M7Read_ISS],
+ (instregex "t2LDRD_(PRE|POST)")>;
+def : InstRW<[WriteLd, M7LoadLatency1, M7SingleIssue, M7Read_ISS],
+ (instregex "t2LDRDi")>;
+
+// Word load / preload
+def : InstRW<[WriteLd],
+ (instregex "t2LDRpc", "t2PL[DI]pci", "tLDRpci")>;
+def : InstRW<[WriteLd, M7Read_ISS],
+ (instregex "t2LDR(i|T)", "t2PL[DI](W)?i", "tLDRi", "tLDRspi")>;
+def : InstRW<[WriteLd, M7Read_ISS, M7Read_ISS],
+ (instregex "t2LDRs", "t2PL[DI](w)?s", "tLDRr")>;
+def : InstRW<[WriteLd, M7BaseUpdate, M7Read_ISS],
+ (instregex "t2LDR_(POST|PRE)")>;
+
+// Stores
+def : InstRW<[M7BaseUpdate, WriteST, M7Read_EX2, M7Read_ISS],
+ (instregex "t2STR(B|H)?_(POST|PRE)")>;
+def : InstRW<[WriteST, M7Read_EX2, M7Read_ISS, M7Read_ISS],
+ (instregex "t2STR(B|H)?s$", "tSTR(B|H)?r$")>;
+def : InstRW<[WriteST, M7Read_EX2, M7Read_ISS],
+ (instregex "t2STR(B|H)?(i|T)", "tSTR(B|H)?i$", "tSTRspi")>;
+
+// TBB/TBH - single-issue only; takes two cycles to issue
+
+def M7TableLoad : SchedWriteRes<[M7UnitLoad]> {
+ let NumMicroOps = 2;
+ let SingleIssue = 1;
+}
+
+def : InstRW<[M7TableLoad, M7Read_ISS, M7Read_ISS], (instregex "t2TB")>;
+
+// VFP loads and stores
+
+def M7LoadSP : SchedWriteRes<[M7UnitLoad, M7UnitVPort]> { let Latency = 1; }
+def M7LoadDP : SchedWriteRes<[M7UnitLoad, M7UnitVPort, M7UnitVPort]> {
+ let Latency = 2;
+ let SingleIssue = 1;
+}
+def M7StoreSP : SchedWriteRes<[M7UnitStore, M7UnitVPort]>;
+def M7StoreDP : SchedWriteRes<[M7UnitStore, M7UnitVPort, M7UnitVPort]> {
+ let SingleIssue = 1;
+}
+
+def : InstRW<[M7LoadSP, M7Read_ISS], (instregex "VLDR(S|H)$")>;
+def : InstRW<[M7LoadDP, M7Read_ISS], (instregex "VLDRD$")>;
+def : InstRW<[M7StoreSP, M7Read_EX3, M7Read_ISS], (instregex "VSTR(S|H)$")>;
+def : InstRW<[M7StoreDP, M7Read_EX3, M7Read_ISS], (instregex "VSTRD$")>;
+
+// Load/store multiples cannot be dual-issued.
+
+def : InstRW<[WriteLd, M7SingleIssue, M7Read_ISS],
+ (instregex "VLDM(S|D|Q)(DB|IA)$")>;
+def : InstRW<[WriteST, M7SingleIssue, M7Read_ISS],
+ (instregex "VSTM(S|D|Q)(DB|IA)$")>;
+def : InstRW<[M7BaseUpdate, WriteLd, M7SingleIssue, M7Read_ISS],
+ (instregex "VLDM(S|D|Q)(DB|IA)_UPD$")>;
+def : InstRW<[M7BaseUpdate, WriteST, M7SingleIssue, M7Read_ISS],
+ (instregex "VSTM(S|D|Q)(DB|IA)_UPD$")>;
+
+//===---------------------------------------------------------------------===//
+// Sched definitions for ALU
+//
+
+// Shifted ALU operands are read a cycle early.
+def M7Ex1ReadNoFastBypass : SchedReadAdvance<-1, [WriteLd, M7LoadLatency1]>;
+
+def : InstRW<[WriteALUsi, M7Ex1ReadNoFastBypass, M7Read_ISS],
+ (instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
+ "t2(SUB|CMP|CMNz|TEQ|TST)rs$",
+ "t2MOVsr(a|l)")>;
+def : InstRW<[WriteALUsi, M7Read_ISS],
+ (instregex "t2MVNs")>;
+
+// Treat pure shift operations (except for RRX) as if they used the EX1
+// shifter but have timing as if they used the EX2 shifter as they usually
+// can choose the EX2 shifter when needed. Will miss a few dual-issue cases,
+// but the results prove to be better than trying to get them exact.
+
+def : InstRW<[M7WriteShift2, M7Read_ISS], (instregex "t2RRX$")>;
+def : InstRW<[WriteALUsi], (instregex "(t|t2)(LSL|LSR|ASR|ROR)")>;
+
+// Instructions that use the shifter, but have normal timing.
+
+def : InstRW<[WriteALUsi,M7Slot0Only], (instregex "t2(BFC|BFI)$")>;
+
+// Instructions which are slot zero only but otherwise normal.
+
+def : InstRW<[WriteALU, M7Slot0Only], (instregex "t2CLZ")>;
+
+// MAC operations that don't have SchedRW set.
+
+def : InstRW<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC], (instregex "t2SML[AS]D")>;
+
+// Divides are special because they stall for their latency, and so look like a
+// single-cycle as far as scheduling opportunities go. By putting WriteALU
+// first, we make the operand latency 1, but keep the instruction latency 7.
+
+def : InstRW<[WriteALU, WriteDIV], (instregex "t2(S|U)DIV")>;
+
+// DSP extension operations
+
+def M7WriteSIMD1 : SchedWriteRes<[M7UnitSIMD, M7UnitALU]> {
+ let Latency = 1;
+ let BeginGroup = 1;
+}
+def M7WriteSIMD2 : SchedWriteRes<[M7UnitSIMD, M7UnitALU]> {
+ let Latency = 2;
+ let BeginGroup = 1;
+}
+def M7WriteShSIMD1 : SchedWriteRes<[M7UnitSIMD, M7UnitALU, M7UnitShift1]> {
+ let Latency = 1;
+ let BeginGroup = 1;
+}
+def M7WriteShSIMD0 : SchedWriteRes<[M7UnitSIMD, M7UnitALU, M7UnitShift1]> {
+ let Latency = 0; // Bypassable out of EX1
+ let BeginGroup = 1;
+}
+def M7WriteShSIMD2 : SchedWriteRes<[M7UnitSIMD, M7UnitALU, M7UnitShift1]> {
+ let Latency = 2;
+ let BeginGroup = 1;
+}
+
+def : InstRW<[M7WriteShSIMD2, M7Read_ISS],
+ (instregex "t2(S|U)SAT")>;
+def : InstRW<[M7WriteSIMD1, ReadALU],
+ (instregex "(t|t2)(S|U)XT(B|H)")>;
+def : InstRW<[M7WriteSIMD1, ReadALU, ReadALU],
+ (instregex "t2(S|SH|U|UH)(ADD16|ADD8|ASX|SAX|SUB16|SUB8)",
+ "t2SEL")>;
+def : InstRW<[M7WriteSIMD2, ReadALU, ReadALU],
+ (instregex "t2(Q|UQ)(ADD|ASX|SAX|SUB)", "t2USAD8")>;
+def : InstRW<[M7WriteShSIMD2, M7Read_ISS, M7Read_ISS],
+ (instregex "t2QD(ADD|SUB)")>;
+def : InstRW<[M7WriteShSIMD0, M7Read_ISS],
+ (instregex "t2(RBIT|REV)", "tREV")>;
+def : InstRW<[M7WriteShSIMD1, M7Read_ISS],
+ (instregex "t2(SBFX|UBFX)")>;
+def : InstRW<[M7WriteShSIMD1, ReadALU, M7Read_ISS],
+ (instregex "t2PKH(BT|TB)", "t2(S|U)XTA")>;
+def : InstRW<[M7WriteSIMD2, ReadALU, ReadALU, M7Read_EX2],
+ (instregex "t2USADA8")>;
+
+// MSR/MRS
+def : InstRW<[M7NonGeneralPurpose], (instregex "MSR", "MRS")>;
+
+//===---------------------------------------------------------------------===//
+// Sched definitions for FP operations
+//
+
+// Effective scheduling latency is really 3 for nearly all FP operations,
+// even if their true latency is higher.
+def M7WriteVFPLatOverride : SchedWriteRes<[]> {
+ let Latency = 3;
+ let NumMicroOps = 0;
+}
+def M7WriteVFPExtraVPort : SchedWriteRes<[M7UnitVPort]> {
+ let Latency = 3;
+ let NumMicroOps = 0;
+}
+
+// Instructions which are missing default schedules.
+def : InstRW<[WriteFPALU32],
+ (instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)S$")>;
+def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64],
+ (instregex "V(ABS|CVT.*|NEG|FP_VMAX.*|FP_VMIN.*|RINT.*)D$")>;
+
+// VCMP
+def M7WriteVCMPS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let Latency = 0; }
+def M7WriteVCMPD : SchedWriteRes<[M7UnitVFP, M7UnitVPort, M7UnitVPort]> {
+ let Latency = 0;
+ let BeginGroup = 1;
+}
+def : InstRW<[M7WriteVCMPS], (instregex "VCMPS$")>;
+def : InstRW<[M7WriteVCMPD], (instregex "VCMPD$")>;
+
+ // VMRS/VMSR
+def M7VMRS : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
+def M7VMSR : SchedWriteRes<[M7UnitVFP, M7UnitVPort]> { let SingleIssue = 1; }
+def : InstRW<[M7VMRS], (instregex "FMSTAT")>;
+def : InstRW<[M7VMSR], (instregex "VMSR")>;
+
+// VSEL cannot bypass in its implied $cpsr operand; model as earlier read
+def : InstRW<[WriteFPALU32, M7Slot0Only, ReadALU, ReadALU, M7Read_ISS],
+ (instregex "VSEL.*S$")>;
+def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64, M7Slot0Only,
+ ReadALU, ReadALU, M7Read_ISS],
+ (instregex "VSEL.*D$")>;
+
+// VMOV
+def : InstRW<[WriteFPMOV],
+ (instregex "VMOV(H|S)$", "FCONST(H|S)")>;
+def : InstRW<[WriteFPMOV, M7WriteVFPExtraVPort, M7Slot0Only],
+ (instregex "VMOVD$")>;
+def : InstRW<[WriteFPMOV, M7WriteVFPExtraVPort, M7Slot0Only],
+ (instregex "FCONSTD")>;
+def : InstRW<[WriteFPMOV, M7WriteVFPExtraVPort, M7SingleIssue],
+ (instregex "VMOV(DRR|RRD|RRS|SRR)")>;
+
+// Larger-latency overrides.
+
+def : InstRW<[M7WriteVFPLatOverride, WriteFPDIV32], (instregex "VDIVS")>;
+def : InstRW<[M7WriteVFPLatOverride, WriteFPDIV64], (instregex "VDIVD")>;
+def : InstRW<[M7WriteVFPLatOverride, WriteFPSQRT32], (instregex "VSQRTS")>;
+def : InstRW<[M7WriteVFPLatOverride, WriteFPSQRT64], (instregex "VSQRTD")>;
+def : InstRW<[M7WriteVFPLatOverride, WriteFPMUL64],
+ (instregex "V(MUL|NMUL)D")>;
+def : InstRW<[M7WriteVFPLatOverride, WriteFPALU64],
+ (instregex "V(ADD|SUB)D")>;
+
+// Multiply-accumulate. Chained SP timing is correct; rest need overrides
+// Double-precision chained MAC stalls the pipeline behind it for 3 cycles,
+// making it appear to have 3 cycle latency for scheduling.
+
+def : InstRW<[M7WriteVFPLatOverride, WriteFPMAC64,
+ ReadFPMAC, ReadFPMUL, ReadFPMUL],
+ (instregex "V(N)?ML(A|S)D$")>;
+
+// Single-precision fused MACs look like latency 5 with advance of 2.
+
+def M7WriteVFPLatOverride5 : SchedWriteRes<[]> {
+ let Latency = 5;
+ let NumMicroOps = 0;
+}
+def M7ReadFPMAC2 : SchedReadAdvance<2>;
+
+def : InstRW<[M7WriteVFPLatOverride5, WriteFPMAC32,
+ M7ReadFPMAC2, ReadFPMUL, ReadFPMUL],
+ (instregex "VF(N)?M(A|S)S$")>;
+
+// Double-precision fused MAC stalls the pipeline behind it for 2 cycles, making
+// it appear to have 3 cycle latency for scheduling.
+
+def : InstRW<[M7WriteVFPLatOverride, WriteFPMAC64,
+ ReadFPMAC, ReadFPMUL, ReadFPMUL],
+ (instregex "VF(N)?M(A|S)D$")>;
+
+} // SchedModel = CortexM7Model
diff --git a/llvm/test/tools/llvm-mca/ARM/m7-fp.s b/llvm/test/tools/llvm-mca/ARM/m7-fp.s
new file mode 100644
index 000000000000..64b293753d47
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m7-fp.s
@@ -0,0 +1,390 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=thumbv7-m.main-none-none-eabi -mcpu=cortex-m7 -mattr=+fp64 -instruction-tables < %s | FileCheck %s
+
+vabs.f32 s0, s2
+vabs.f64 d0, d2
+vadd.f32 s0, s2, s1
+vadd.f64 d0, d2, d1
+vcmp.f32 s1, s2
+vcmp.f64 d1, d2
+vcvt.f32.f64 s1, d2
+vcvt.f64.f32 d1, s1
+vcvt.f32.u16 s1, s2, #8
+vcvt.f32.s16 s1, s2, #8
+vcvt.f32.u32 s1, s2, #8
+vcvt.f32.s32 s1, s2, #8
+vcvt.u16.f32 s1, s2, #8
+vcvt.s16.f32 s1, s2, #8
+vcvt.u32.f32 s1, s2, #8
+vcvt.s32.f32 s1, s2, #8
+vcvt.f64.u16 d1, d2, #8
+vcvt.f64.s16 d1, d2, #8
+vcvt.f64.u32 d1, d2, #8
+vcvt.f64.s32 d1, d2, #8
+vcvt.u16.f64 d1, d2, #8
+vcvt.s16.f64 d1, d2, #8
+vcvt.u32.f64 d1, d2, #8
+vcvt.s32.f64 d1, d2, #8
+vcvt.u32.f32 s1, s2
+vcvt.s32.f32 s1, s2
+vcvt.u32.f64 s1, d2
+vcvt.s32.f64 s1, d2
+vcvt.f32.u32 s1, s2
+vcvt.f32.s32 s1, s2
+vcvt.f64.u32 d1, s2
+vcvt.f64.s32 d1, s2
+vcvta.u32.f32 s1, s2
+vcvta.s32.f32 s1, s2
+vcvta.u32.f64 s1, d2
+vcvta.s32.f64 s1, d2
+vcvtm.u32.f32 s1, s2
+vcvtm.s32.f32 s1, s2
+vcvtm.u32.f64 s1, d2
+vcvtm.s32.f64 s1, d2
+vcvtn.u32.f32 s1, s2
+vcvtn.s32.f32 s1, s2
+vcvtn.u32.f64 s1, d2
+vcvtn.s32.f64 s1, d2
+vcvtp.u32.f32 s1, s2
+vcvtp.s32.f32 s1, s2
+vcvtp.u32.f64 s1, d2
+vcvtp.s32.f64 s1, d2
+vcvtb.f32.f16 s1, s2
+vcvtb.f16.f32 s1, s2
+vcvtr.u32.f32 s1, s2
+vcvtr.s32.f32 s1, s2
+vcvtr.u32.f64 s1, d2
+vcvtr.s32.f64 s1, d2
+vcvtt.f16.f32 s1, s2
+vcvtt.f32.f16 s1, s2
+vdiv.f32 s0, s2, s1
+vdiv.f64 d0, d2, d1
+vfma.f32 s0, s2, s1
+vfma.f64 d0, d2, d1
+vfms.f32 s0, s2, s1
+vfms.f64 d0, d2, d1
+vfnma.f32 s0, s2, s1
+vfnma.f64 d0, d2, d1
+vfnms.f32 s0, s2, s1
+vfnms.f64 d0, d2, d1
+vmaxnm.f32 s0, s2, s1
+vmaxnm.f64 d0, d2, d1
+vminnm.f32 s0, s2, s1
+vminnm.f64 d0, d2, d1
+vmla.f32 s0, s2, s1
+vmla.f64 d0, d2, d1
+vmls.f32 s0, s2, s1
+vmls.f64 d0, d2, d1
+vmov.f32 s0, r1
+vmov.f32 r0, s1
+vmov.f64 d0, r1, r2
+vmov.f64 r0, r1, d1
+vmov s0, s1, r0, r1
+vmov r0, r1, s0, s1
+vmov.f32 s0, #1.0
+vmov.f64 d0, #1.0
+vmov.f32 s0, s1
+vmov.f64 d0, d1
+vmul.f32 s0, s2, s1
+vmul.f64 d0, d2, d1
+vneg.f32 s0, s2
+vneg.f64 d0, d2
+vnmla.f32 s0, s2, s1
+vnmla.f64 d0, d2, d1
+vnmls.f32 s0, s2, s1
+vnmls.f64 d0, d2, d1
+vnmul.f32 s0, s2, s1
+vnmul.f64 d0, d2, d1
+vrinta.f32.f32 s0, s2
+vrinta.f64.f64 d0, d2
+vrintm.f32.f32 s0, s2
+vrintm.f64.f64 d0, d2
+vrintn.f32.f32 s0, s2
+vrintn.f64.f64 d0, d2
+vrintp.f32.f32 s0, s2
+vrintp.f64.f64 d0, d2
+vrintr.f32.f32 s0, s2
+vrintr.f64.f64 d0, d2
+vrintz.f32.f32 s0, s2
+vrintz.f64.f64 d0, d2
+vrintx.f32.f32 s0, s2
+vrintx.f64.f64 d0, d2
+vseleq.f32 s0, s2, s1
+vseleq.f64 d0, d2, d1
+vsqrt.f32 s0, s2
+vsqrt.f64 d0, d2
+vsub.f32 s0, s2, s1
+vsub.f64 d0, d2, d1
+
+vldr.f64 d0, [r0]
+vldr.f32 s0, [r0]
+vstr.f64 d0, [r0]
+vstr.f32 s0, [r0]
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 3 1.00 vabs.f32 s0, s2
+# CHECK-NEXT: 1 4 1.00 vabs.f64 d0, d2
+# CHECK-NEXT: 1 3 1.00 vadd.f32 s0, s2, s1
+# CHECK-NEXT: 1 4 1.00 vadd.f64 d0, d2, d1
+# CHECK-NEXT: 1 0 1.00 vcmp.f32 s1, s2
+# CHECK-NEXT: 1 0 1.00 vcmp.f64 d1, d2
+# CHECK-NEXT: 1 4 1.00 vcvt.f32.f64 s1, d2
+# CHECK-NEXT: 1 3 1.00 vcvt.f64.f32 d1, s1
+# CHECK-NEXT: 1 3 1.00 vcvt.f32.u16 s1, s1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.f32.s16 s1, s1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.f32.u32 s1, s1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.f32.s32 s1, s1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.u16.f32 s1, s1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.s16.f32 s1, s1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.u32.f32 s1, s1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.s32.f32 s1, s1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.f64.u16 d1, d1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.f64.s16 d1, d1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.f64.u32 d1, d1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.f64.s32 d1, d1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.u16.f64 d1, d1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.s16.f64 d1, d1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.u32.f64 d1, d1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.s32.f64 d1, d1, #8
+# CHECK-NEXT: 1 3 1.00 vcvt.u32.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvt.s32.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvt.u32.f64 s1, d2
+# CHECK-NEXT: 1 3 1.00 vcvt.s32.f64 s1, d2
+# CHECK-NEXT: 1 3 1.00 vcvt.f32.u32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvt.f32.s32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvt.f64.u32 d1, s2
+# CHECK-NEXT: 1 3 1.00 vcvt.f64.s32 d1, s2
+# CHECK-NEXT: 1 3 1.00 vcvta.u32.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvta.s32.f32 s1, s2
+# CHECK-NEXT: 1 4 1.00 vcvta.u32.f64 s1, d2
+# CHECK-NEXT: 1 4 1.00 vcvta.s32.f64 s1, d2
+# CHECK-NEXT: 1 3 1.00 vcvtm.u32.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvtm.s32.f32 s1, s2
+# CHECK-NEXT: 1 4 1.00 vcvtm.u32.f64 s1, d2
+# CHECK-NEXT: 1 4 1.00 vcvtm.s32.f64 s1, d2
+# CHECK-NEXT: 1 3 1.00 vcvtn.u32.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvtn.s32.f32 s1, s2
+# CHECK-NEXT: 1 4 1.00 vcvtn.u32.f64 s1, d2
+# CHECK-NEXT: 1 4 1.00 vcvtn.s32.f64 s1, d2
+# CHECK-NEXT: 1 3 1.00 vcvtp.u32.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvtp.s32.f32 s1, s2
+# CHECK-NEXT: 1 4 1.00 vcvtp.u32.f64 s1, d2
+# CHECK-NEXT: 1 4 1.00 vcvtp.s32.f64 s1, d2
+# CHECK-NEXT: 1 3 1.00 vcvtb.f32.f16 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvtb.f16.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvtr.u32.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvtr.s32.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvtr.u32.f64 s1, d2
+# CHECK-NEXT: 1 3 1.00 vcvtr.s32.f64 s1, d2
+# CHECK-NEXT: 1 3 1.00 vcvtt.f16.f32 s1, s2
+# CHECK-NEXT: 1 3 1.00 vcvtt.f32.f16 s1, s2
+# CHECK-NEXT: 1 16 1.00 vdiv.f32 s0, s2, s1
+# CHECK-NEXT: 1 30 1.00 vdiv.f64 d0, d2, d1
+# CHECK-NEXT: 1 6 1.00 vfma.f32 s0, s2, s1
+# CHECK-NEXT: 1 11 1.00 vfma.f64 d0, d2, d1
+# CHECK-NEXT: 1 6 1.00 vfms.f32 s0, s2, s1
+# CHECK-NEXT: 1 11 1.00 vfms.f64 d0, d2, d1
+# CHECK-NEXT: 1 6 1.00 vfnma.f32 s0, s2, s1
+# CHECK-NEXT: 1 11 1.00 vfnma.f64 d0, d2, d1
+# CHECK-NEXT: 1 6 1.00 vfnms.f32 s0, s2, s1
+# CHECK-NEXT: 1 11 1.00 vfnms.f64 d0, d2, d1
+# CHECK-NEXT: 1 3 1.00 vmaxnm.f32 s0, s2, s1
+# CHECK-NEXT: 1 4 1.00 vmaxnm.f64 d0, d2, d1
+# CHECK-NEXT: 1 3 1.00 vminnm.f32 s0, s2, s1
+# CHECK-NEXT: 1 4 1.00 vminnm.f64 d0, d2, d1
+# CHECK-NEXT: 1 6 1.00 vmla.f32 s0, s2, s1
+# CHECK-NEXT: 1 11 1.00 vmla.f64 d0, d2, d1
+# CHECK-NEXT: 1 6 1.00 vmls.f32 s0, s2, s1
+# CHECK-NEXT: 1 11 1.00 vmls.f64 d0, d2, d1
+# CHECK-NEXT: 1 3 0.50 vmov s0, r1
+# CHECK-NEXT: 1 3 0.50 vmov r0, s1
+# CHECK-NEXT: 1 3 1.00 vmov d0, r1, r2
+# CHECK-NEXT: 1 3 1.00 vmov r0, r1, d1
+# CHECK-NEXT: 1 3 1.00 vmov s0, s1, r0, r1
+# CHECK-NEXT: 1 3 1.00 vmov r0, r1, s0, s1
+# CHECK-NEXT: 1 3 0.50 vmov.f32 s0, #1.000000e+00
+# CHECK-NEXT: 1 3 1.00 vmov.f64 d0, #1.000000e+00
+# CHECK-NEXT: 1 3 0.50 vmov.f32 s0, s1
+# CHECK-NEXT: 1 3 1.00 vmov.f64 d0, d1
+# CHECK-NEXT: 1 3 1.00 vmul.f32 s0, s2, s1
+# CHECK-NEXT: 1 7 1.00 vmul.f64 d0, d2, d1
+# CHECK-NEXT: 1 3 1.00 vneg.f32 s0, s2
+# CHECK-NEXT: 1 4 1.00 vneg.f64 d0, d2
+# CHECK-NEXT: 1 6 1.00 vnmla.f32 s0, s2, s1
+# CHECK-NEXT: 1 11 1.00 vnmla.f64 d0, d2, d1
+# CHECK-NEXT: 1 6 1.00 vnmls.f32 s0, s2, s1
+# CHECK-NEXT: 1 11 1.00 vnmls.f64 d0, d2, d1
+# CHECK-NEXT: 1 3 1.00 vnmul.f32 s0, s2, s1
+# CHECK-NEXT: 1 7 1.00 vnmul.f64 d0, d2, d1
+# CHECK-NEXT: 1 3 1.00 vrinta.f32 s0, s2
+# CHECK-NEXT: 1 4 1.00 vrinta.f64 d0, d2
+# CHECK-NEXT: 1 3 1.00 vrintm.f32 s0, s2
+# CHECK-NEXT: 1 4 1.00 vrintm.f64 d0, d2
+# CHECK-NEXT: 1 3 1.00 vrintn.f32 s0, s2
+# CHECK-NEXT: 1 4 1.00 vrintn.f64 d0, d2
+# CHECK-NEXT: 1 3 1.00 vrintp.f32 s0, s2
+# CHECK-NEXT: 1 4 1.00 vrintp.f64 d0, d2
+# CHECK-NEXT: 1 3 1.00 vrintr.f32 s0, s2
+# CHECK-NEXT: 1 4 1.00 vrintr.f64 d0, d2
+# CHECK-NEXT: 1 3 1.00 vrintz.f32 s0, s2
+# CHECK-NEXT: 1 4 1.00 vrintz.f64 d0, d2
+# CHECK-NEXT: 1 3 1.00 vrintx.f32 s0, s2
+# CHECK-NEXT: 1 4 1.00 vrintx.f64 d0, d2
+# CHECK-NEXT: 1 4 1.00 vseleq.f32 s0, s2, s1
+# CHECK-NEXT: 1 5 1.00 vseleq.f64 d0, d2, d1
+# CHECK-NEXT: 1 16 1.00 vsqrt.f32 s0, s2
+# CHECK-NEXT: 1 30 1.00 vsqrt.f64 d0, d2
+# CHECK-NEXT: 1 3 1.00 vsub.f32 s0, s2, s1
+# CHECK-NEXT: 1 4 1.00 vsub.f64 d0, d2, d1
+# CHECK-NEXT: 1 3 1.00 * vldr d0, [r0]
+# CHECK-NEXT: 1 2 0.50 * vldr s0, [r0]
+# CHECK-NEXT: 1 2 1.00 * vstr d0, [r0]
+# CHECK-NEXT: 1 2 1.00 * vstr s0, [r0]
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - M7UnitALU
+# CHECK-NEXT: [0.1] - M7UnitALU
+# CHECK-NEXT: [1] - M7UnitBranch
+# CHECK-NEXT: [2.0] - M7UnitLoad
+# CHECK-NEXT: [2.1] - M7UnitLoad
+# CHECK-NEXT: [3] - M7UnitMAC
+# CHECK-NEXT: [4] - M7UnitSIMD
+# CHECK-NEXT: [5] - M7UnitShift1
+# CHECK-NEXT: [6] - M7UnitShift2
+# CHECK-NEXT: [7] - M7UnitStore
+# CHECK-NEXT: [8] - M7UnitVFP
+# CHECK-NEXT: [9.0] - M7UnitVPort
+# CHECK-NEXT: [9.1] - M7UnitVPort
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1]
+# CHECK-NEXT: - - - 1.00 1.00 - - - - 2.00 104.00 81.00 81.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] Instructions:
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vabs.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vabs.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vadd.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vadd.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcmp.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcmp.f64 d1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvt.f32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.f32 d1, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s16 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u16.f32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s16.f32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f32 s1, s1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.u16 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.s16 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.u32 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.s32 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u16.f64 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s16.f64 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f64 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f64 d1, d1, #8
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.u32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f32.s32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.u32 d1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvt.f64.s32 d1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvta.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvta.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvta.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtm.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtm.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtm.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtn.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtn.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtn.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtp.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtp.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vcvtp.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtb.f32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtb.f16.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.u32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.s32.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.u32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtr.s32.f64 s1, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtt.f16.f32 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vcvtt.f32.f16 s1, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vdiv.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vdiv.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfma.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfma.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfms.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfms.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnma.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfnma.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vfnms.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vfnms.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmaxnm.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmaxnm.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vminnm.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vminnm.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmla.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmla.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmls.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmls.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov s0, r1
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov r0, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov d0, r1, r2
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov r0, r1, d1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov s0, s1, r0, r1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov r0, r1, s0, s1
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f32 s0, #1.000000e+00
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov.f64 d0, #1.000000e+00
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vmov.f32 s0, s1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmov.f64 d0, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vmul.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vmul.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vneg.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vneg.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmla.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vnmla.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmls.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vnmls.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vnmul.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vnmul.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrinta.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrinta.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintm.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintm.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintn.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintn.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintp.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintp.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintr.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintr.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintz.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintz.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vrintx.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vrintx.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vseleq.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vseleq.f64 d0, d2, d1
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsqrt.f32 s0, s2
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vsqrt.f64 d0, d2
+# CHECK-NEXT: - - - - - - - - - - 1.00 0.50 0.50 vsub.f32 s0, s2, s1
+# CHECK-NEXT: - - - - - - - - - - 1.00 1.00 1.00 vsub.f64 d0, d2, d1
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - 1.00 1.00 vldr d0, [r0]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - 0.50 0.50 vldr s0, [r0]
+# CHECK-NEXT: - - - - - - - - - 1.00 - 1.00 1.00 vstr d0, [r0]
+# CHECK-NEXT: - - - - - - - - - 1.00 - 0.50 0.50 vstr s0, [r0]
diff --git a/llvm/test/tools/llvm-mca/ARM/m7-int.s b/llvm/test/tools/llvm-mca/ARM/m7-int.s
new file mode 100644
index 000000000000..4768dcf296bc
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m7-int.s
@@ -0,0 +1,1299 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=thumbv7-m.main-none-none-eabi -mcpu=cortex-m7 -instruction-tables < %s | FileCheck %s
+
+adc r0, r1, #0
+adcs r0, r1, #0
+adcs r0, r1
+adc.w r0, r1, r2
+adcs.w r0, r1, r2
+adc.w r0, r1, r2, LSL #1
+adcs.w r0, r1, r2, LSL #1
+adds r0, r1, #1
+adds r0, #42
+add.w r0, r1, #1
+adds.w r0, r1, #1
+addw r0, r1, #1
+adds r0, r1, r2
+add r0, r1
+add.w r0, r1, r2
+adds.w r0, r1, r2
+add.w r0, r1, r2, LSL #1
+adds.w r0, r1, r2, LSL #1
+add r0, sp, #1
+add sp, sp, #1
+add.w r0, sp, #1
+adds.w r0, sp, #1
+addw r0, sp, #1
+add r0, sp, r0
+add sp, r1
+add.w r0, sp, r1
+adds.w r0, sp, r1
+add.w r0, sp, r1, LSL #1
+adds.w r0, sp, r1, LSL #1
+adr r0, #-6
+and r0, r1, #1
+ands r0, r1, #1
+ands r1, r0
+and.w r0, r1, r2
+ands.w r0, r1, r2
+and.w r0, r1, r2, LSL #1
+ands.w r0, r1, r2, LSL #1
+asrs r0, r1, #1
+asr.w r0, r1, #1
+asrs.w r0, r1, #1
+asrs r0, r1
+asr.w r0, r1, r2
+asrs.w r0, r1, r2
+bfc r0, #1, #2
+bfi r0, r1, #1, #2
+bic r0, r1, #1
+bics r0, r1, #1
+bics r0, r1
+bic.w r0, r1, r2
+bics.w r0, r1, r2
+bic.w r0, r1, r2, LSL #1
+bics.w r0, r1, r2, LSL #1
+bkpt #1
+clrex
+clz r0, r1
+cmn r0, #1
+cmn r0, r1
+cmn.w r0, r1
+cmn.w r0, r1, LSL #1
+cmp r0, #1
+cmp.w r0, #1
+cmp r0, r1
+cmp r0, r10
+cmp.w r0, r1
+cmp.w r0, r1, LSL #1
+#cpsie if
+#dbg #1
+dmb
+dsb
+eor r0, r1, #1
+eors r0, r1, #1
+eors r0, r1
+eor.w r0, r1, r2
+eors.w r0, r1, r2
+eor.w r0, r1, r2, LSL #1
+eors.w r0, r1, r2, LSL #1
+isb
+#it eq
+#adceq r0, r1, #1
+ldm r0!, {r1}
+ldm r0, {r1}
+ldm.w r0, {r1}
+ldm.w r0!, {r1}
+ldmdb r0, {r1}
+ldmdb r0!, {r1}
+ldr r0, [r1, #4]
+ldr r0, [sp, #4]
+ldr.w r0, [r1, #4]
+ldr r0, [r1, #-1]
+ldr r0, [r1], #1
+ldr r0, [r1, #1]!
+ldr r0, #4
+ldr.w r0, #4
+ldr r0, [r1, r2]
+ldr.w r0, [r1, r2]
+ldr.w r0, [r1, r2, LSL #1]
+ldrb r0, [r1, #1]
+ldrb.w r0, [r1, #1]
+ldrb r0, [r1, #-1]
+ldrb r0, [r1], #1
+ldrb r0, [r1, #1]!
+ldrb r0, #4
+ldrb r0, [r1, r2]
+ldrb.w r0, [r1, r2]
+ldrb.w r0, [r1, r2, LSL #1]
+ldrbt r0, [r1, #1]
+ldrd r0, r2, [r1]
+ldrd r0, r2, [r1, #-4]
+ldrd r0, r2, [r1], #4
+ldrd r0, r2, [r1, #4]!
+ldrd r0, r2, next
+next:
+ldrex r0, [r1]
+ldrex r0, [r1, #4]
+ldrexb r0, [r1]
+ldrexh r0, [r1]
+ldrh r0, [r1, #2]
+ldrh.w r0, [r1, #1]
+ldrh r0, [r1, #-1]
+ldrh r0, [r1], #1
+ldrh r0, [r1, #1]!
+ldrh r0, #4
+ldrh r0, [r1, r2]
+ldrh.w r0, [r1, r2]
+ldrh.w r0, [r1, r2, LSL #1]
+ldrht r0, [r1, #1]
+ldrsb r0, [r1, #1]
+ldrsb r0, [r1, #-1]
+ldrsb r0, [r1], #1
+ldrsb r0, [r1, #1]!
+ldrsb r0, #4
+ldrsb r0, [r1, r2]
+ldrsb.w r0, [r1, r2]
+ldrsb.w r0, [r1, r2, LSL #1]
+ldrsbt r0, [r1, #1]
+ldrsh r0, [r1, #2]
+ldrsh r0, [r1, #-1]
+ldrsh r0, [r1], #1
+ldrsh r0, [r1, #1]!
+ldrsh r0, #4
+ldrsh r0, [r1, r2]
+ldrsh.w r0, [r1, r2]
+ldrsh.w r0, [r1, r2, LSL #1]
+ldrsht r0, [r1, #1]
+ldrt r0, [r1, #1]
+lsls r0, r1, #1
+lsl.w r0, r1, #1
+lsls.w r0, r1, #1
+lsls r0, r1
+lsl.w r0, r1, r2
+lsls.w r0, r1, r2
+lsrs r0, r1, #1
+lsr.w r0, r1, #1
+lsrs.w r0, r1, #1
+lsrs r0, r1
+lsr.w r0, r1, r2
+lsrs.w r0, r1, r2
+mla r0, r1, r2, r3
+mls r0, r1, r2, r3
+movs r0, #1
+mov.w r0, #1
+movs.w r0, #1
+movw r0, #1
+mov r0, r1
+#movs r0, r1
+mov.w r0, r1
+movs.w r0, r1
+movt r0, #1
+mrs r0, apsr
+msr apsr, r0
+muls r1, r2, r1
+mul r0, r1, r2
+mvn r0, #1
+mvns r0, #1
+mvns r0, r1
+mvn.w r0, r1
+mvns.w r0, r1
+mvn.w r0, r1, LSL #1
+mvns.w r0, r1, LSL #1
+nop
+nop.w
+orn r0, r1, #1
+orns r0, r1, #1
+orn r0, r1, r2
+orns r0, r1, r2
+orn r0, r1, r2, LSL #1
+orns r0, r1, r2, LSL #1
+orr r0, r1, #1
+orrs r0, r1, #1
+orrs r0, r1
+orr r0, r1, r2
+orrs r0, r1, r2
+orr r0, r1, r2, LSL #1
+orrs r0, r1, r2, LSL #1
+pkhbt r0, r1, r2
+pkhbt r0, r1, r2, LSL #1
+pkhtb r0, r1, r2
+pkhtb r0, r1, r2, ASR #1
+pop { r0 }
+pop.w { r0, r1 }
+pop.w { r0 }
+push { r0 }
+push.w { r0, r1 }
+push.w { r0 }
+qadd r0, r1, r2
+qadd16 r0, r1, r2
+qadd8 r0, r1, r2
+qasx r0, r1, r2
+qdadd r0, r1, r2
+qdsub r0, r1, r2
+qsax r0, r1, r2
+qsub r0, r1, r2
+qsub16 r0, r1, r2
+qsub8 r0, r1, r2
+rbit r0, r1
+rev r0, r1
+rev.w r0, r1
+rev16 r0, r1
+rev16.w r0, r1
+revsh r0, r1
+revsh.w r0, r1
+ror r0, r1, #1
+rors r0, r1, #1
+rors r0, r1
+ror.w r0, r1, r2
+rors.w r0, r1, r2
+rrx r0, r1
+rrxs r0, r1
+rsbs r0, r1, #0
+rsb.w r0, r1, #1
+rsbs.w r0, r1, #1
+rsb r0, r1, r2
+rsbs r0, r1, r2
+rsb r0, r1, r2, LSL #1
+rsbs r0, r1, r2, LSL #1
+sadd16 r0, r1, r2
+sadd8 r0, r1, r2
+sasx r0, r1, r2
+sbc r0, r1, #1
+sbcs r0, r1, #1
+sbcs r0, r1
+sbc r0, r1, r2
+sbcs r0, r1, r2
+sbc r0, r1, r2, LSL #1
+sbcs r0, r1, r2, LSL #1
+sbfx r0, r1, #1, #2
+sdiv r0, r1, r2
+sel r0, r1, r2
+#sev
+shadd16 r0, r1, r2
+shadd8 r0, r1, r2
+shasx r0, r1, r2
+shsax r0, r1, r2
+shsub16 r0, r1, r2
+shsub8 r0, r1, r2
+smlabb r0, r1, r2, r3
+smlabt r0, r1, r2, r3
+smlatb r0, r1, r2, r3
+smlatt r0, r1, r2, r3
+smlad r0, r1, r2, r3
+smladx r0, r1, r2, r3
+smlal r0, r1, r2, r3
+smlalbb r0, r1, r2, r3
+smlalbt r0, r1, r2, r3
+smlaltb r0, r1, r2, r3
+smlaltt r0, r1, r2, r3
+smlald r0, r1, r2, r3
+smlaldx r0, r1, r2, r3
+smlawb r0, r1, r2, r3
+smlawt r0, r1, r2, r3
+smlsd r0, r1, r2, r3
+smlsdx r0, r1, r2, r3
+smlsld r0, r1, r2, r3
+smlsldx r0, r1, r2, r3
+smmla r0, r1, r2, r3
+smmlar r0, r1, r2, r3
+smmls r0, r1, r2, r3
+smmlsr r0, r1, r2, r3
+smmul r0, r1, r2
+smmulr r0, r1, r2
+smuad r0, r1, r2
+smuadx r0, r1, r2
+smulbb r0, r1, r2
+smulbt r0, r1, r2
+smultb r0, r1, r2
+smultt r0, r1, r2
+smull r0, r1, r2, r3
+smulwb r0, r1, r2
+smulwt r0, r1, r2
+smusd r0, r1, r2
+smusdx r0, r1, r2
+ssat r0, #1, r2
+ssat r0, #1, r2, LSL #1
+ssat16 r0, #1, r1
+ssax r0, r1, r2
+ssub16 r0, r1, r2
+ssub8 r0, r1, r2
+stm r0!, { r1 }
+stm.w r0, { r1 }
+stm.w r0!, { r1 }
+stmdb r0, { r1 }
+stmdb r0!, { r1 }
+str r0, [ r1 ]
+str r0, [ r1, #4 ]
+str r0, [ sp, #4 ]
+str.w r0, [ r1, #1 ]
+str r0, [ r1, #-1 ]
+str r0, [ r1 ], #1
+#str r0, [ r1, #1 ]!
+str r0, [ r1, r2 ]
+str.w r0, [ r1, r2 ]
+str.w r0, [ r1, r2, LSL #1 ]
+strb r0, [ r1 ]
+strb r0, [ r1, #1 ]
+strb.w r0, [ r1, #1 ]
+strb r0, [ r1, #-1 ]
+strb r0, [ r1 ], #1
+strb r0, [ r1, #1 ]!
+strb r0, [ r1, r2 ]
+strb.w r0, [ r1, r2 ]
+strb.w r0, [ r1, r2, LSL #1 ]
+strbt r0, [ r1, #1 ]
+strd r0, r1, [ r2, #4 ]
+strd r0, r1, [ r2 ], #4
+strd r0, r1, [ r2, #4 ]!
+strex r0, r1, [ r2 ]
+strex r0, r1, [ r2, #4 ]
+strexb r0, r1, [ r2 ]
+strexh r0, r1, [ r2 ]
+strh r0, [ r1 ]
+strh r0, [ r1, #2 ]
+strh.w r0, [ r1, #2 ]
+strh r0, [ r1, #-1 ]
+strh r0, [ r1 ], #1
+strh r0, [ r1, #1 ]!
+strh r0, [ r1, r2 ]
+strh.w r0, [ r1, r2 ]
+strh.w r0, [ r1, r2, LSL #1 ]
+strht r0, [r1, #1 ]
+strt r0, [r1, #1 ]
+subs r0, r1, #1
+subs r0, #1
+sub.w r0, r1, #1
+subs.w r0, r1, #1
+subw r0, r1, #1
+subs r0, r1, r2
+sub.w r0, r1, r2
+subs.w r0, r1, r2
+sub.w r0, r1, r2, LSL #1
+subs.w r0, r1, r2, LSL #1
+sub sp, sp, #4
+sub.w r0, sp, #1
+subs.w r0, sp, #1
+subw r0, sp, #1
+sub r0, sp, r1
+subs r0, sp, r1
+sub r0, sp, r1, LSL #1
+subs r0, sp, r1, LSL #1
+#svc #1 ; treated as a call
+sxtab r0, r1, r2
+sxtab r0, r1, r2, ROR #8
+sxtab16 r0, r1, r2
+sxtab16 r0, r1, r2, ROR #8
+sxtah r0, r1, r2
+sxtah r0, r1, r2, ROR #8
+sxtb r0, r1
+sxtb.w r0, r1
+sxtb.w r0, r1, ROR #8
+sxtb16 r0, r1
+sxtb16 r0, r1, ROR #8
+sxth r0, r1
+sxth.w r0, r1
+sxth.w r0, r1, ROR #8
+tbb [r0, r1]
+tbh [r0, r1, LSL #1]
+teq r0, #1
+teq r0, r1
+teq r0, r1, LSL #1
+tst r0, #1
+tst r0, r1
+tst.w r0, r1
+tst.w r0, r1, LSL #1
+uadd16 r0, r1, r2
+uadd8 r0, r1, r2
+uasx r0, r1, r2
+ubfx r0, r1, #1, #2
+#udf #1
+udiv r0, r1, r2
+uhadd16 r0, r1, r2
+uhadd8 r0, r1, r2
+uhasx r0, r1, r2
+uhsax r0, r1, r2
+uhsub16 r0, r1, r2
+uhsub8 r0, r1, r2
+umaal r0, r1, r2, r3
+umlal r0, r1, r2, r3
+umull r0, r1, r2, r3
+uqadd16 r0, r1, r2
+uqadd8 r0, r1, r2
+uqasx r0, r1, r2
+uqsax r0, r1, r2
+uqsub16 r0, r1, r2
+uqsub8 r0, r1, r2
+usad8 r0, r1, r2
+usada8 r0, r1, r2, r3
+usat r0, #1, r1
+usat r0, #1, r1, LSL #1
+usat16 r0, #1, r1
+usax r0, r1, r2
+usub16 r0, r1, r2
+usub8 r0, r1, r2
+uxtab r0, r1, r2
+uxtab r0, r1, r2, ROR #8
+uxtab16 r0, r1, r2
+uxtab16 r0, r1, r2, ROR #8
+uxtah r0, r1, r2
+uxtah r0, r1, r2, ROR #8
+uxtb r0, r1
+uxtb.w r0, r1
+uxtb.w r0, r1, ROR #8
+uxtb16 r0, r1
+uxtb16 r0, r1, ROR #8
+uxth r0, r1
+uxth.w r0, r1
+uxth.w r0, r1, ROR #8
+wfe
+wfi
+yield
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 adc r0, r1, #0
+# CHECK-NEXT: 1 1 0.50 adcs r0, r1, #0
+# CHECK-NEXT: 1 1 0.50 U adcs r0, r1
+# CHECK-NEXT: 1 1 0.50 adc.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 adcs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 adc.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 adcs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 0.50 adds r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 adds r0, #42
+# CHECK-NEXT: 1 1 0.50 add.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 adds.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 addw r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 adds r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 add r0, r1
+# CHECK-NEXT: 1 1 0.50 add.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 adds.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 add.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 adds.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 0.50 add.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 U add.w sp, sp, #1
+# CHECK-NEXT: 1 1 0.50 add.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 adds.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 addw r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 U add r0, sp, r0
+# CHECK-NEXT: 1 1 0.50 U add sp, r1
+# CHECK-NEXT: 1 1 0.50 add.w r0, sp, r1
+# CHECK-NEXT: 1 1 0.50 adds.w r0, sp, r1
+# CHECK-NEXT: 1 2 1.00 add.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 1 2 1.00 adds.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 1 1 0.50 U adr.w r0, #-6
+# CHECK-NEXT: 1 1 0.50 and r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 ands r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 ands r1, r0
+# CHECK-NEXT: 1 1 0.50 and.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 ands.w r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 and.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 1.00 ands.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 1.00 asrs r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 asr.w r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 asrs.w r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 asrs r0, r1
+# CHECK-NEXT: 1 1 1.00 asr.w r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 asrs.w r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 bfc r0, #1, #2
+# CHECK-NEXT: 1 1 1.00 bfi r0, r1, #1, #2
+# CHECK-NEXT: 1 1 0.50 bic r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 bics r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 bics r0, r1
+# CHECK-NEXT: 1 1 0.50 bic.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 bics.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 bic.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 bics.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 3 0.50 U bkpt #1
+# CHECK-NEXT: 1 3 0.50 * * U clrex
+# CHECK-NEXT: 1 1 0.50 clz r0, r1
+# CHECK-NEXT: 1 1 0.50 cmn.w r0, #1
+# CHECK-NEXT: 1 1 0.50 cmn r0, r1
+# CHECK-NEXT: 1 1 0.50 cmn.w r0, r1
+# CHECK-NEXT: 1 2 1.00 cmn.w r0, r1, lsl #1
+# CHECK-NEXT: 1 1 0.50 cmp r0, #1
+# CHECK-NEXT: 1 1 0.50 cmp.w r0, #1
+# CHECK-NEXT: 1 1 0.50 cmp r0, r1
+# CHECK-NEXT: 1 1 0.50 U cmp r0, r10
+# CHECK-NEXT: 1 1 0.50 cmp.w r0, r1
+# CHECK-NEXT: 1 2 1.00 cmp.w r0, r1, lsl #1
+# CHECK-NEXT: 1 3 0.50 * * U dmb sy
+# CHECK-NEXT: 1 3 0.50 * * U dsb sy
+# CHECK-NEXT: 1 1 0.50 eor r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 eors r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 eors r0, r1
+# CHECK-NEXT: 1 1 0.50 eor.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 eors.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 eor.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 eors.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 3 0.50 * * U isb sy
+# CHECK-NEXT: 1 2 0.50 * ldm r0!, {r1}
+# CHECK-NEXT: 1 2 0.50 * ldm.w r0, {r1}
+# CHECK-NEXT: 1 2 0.50 * ldm.w r0, {r1}
+# CHECK-NEXT: 1 2 0.50 * ldr r1, [r0], #4
+# CHECK-NEXT: 1 2 0.50 * ldmdb r0, {r1}
+# CHECK-NEXT: 1 2 0.50 * ldmdb r0!, {r1}
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1, #4]
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [sp, #4]
+# CHECK-NEXT: 1 2 0.50 * ldr.w r0, [r1, #4]
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1, #-1]
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1], #1
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1, #1]!
+# CHECK-NEXT: 1 1 0.50 * ldr r0, [pc, #4]
+# CHECK-NEXT: 1 1 0.50 * ldr.w r0, [pc, #4]
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [r1, r2]
+# CHECK-NEXT: 1 2 0.50 * ldr.w r0, [r1, r2]
+# CHECK-NEXT: 1 2 0.50 * ldr.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrb.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1, #1]!
+# CHECK-NEXT: 1 2 0.50 * ldrb.w r0, [pc, #4]
+# CHECK-NEXT: 1 3 0.50 * ldrb r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrb.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U ldrbt r0, [r1, #1]
+# CHECK-NEXT: 1 2 0.50 * ldrd r0, r2, [r1]
+# CHECK-NEXT: 1 2 0.50 * ldrd r0, r2, [r1, #-4]
+# CHECK-NEXT: 1 2 0.50 * ldrd r0, r2, [r1], #4
+# CHECK-NEXT: 1 2 0.50 * ldrd r0, r2, [r1, #4]!
+# CHECK-NEXT: 1 2 0.50 * ldrd r0, r2, next
+# CHECK-NEXT: 1 2 0.50 * * U ldrex r0, [r1]
+# CHECK-NEXT: 1 2 0.50 * * U ldrex r0, [r1, #4]
+# CHECK-NEXT: 1 3 0.50 * * U ldrexb r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * * U ldrexh r0, [r1]
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1, #2]
+# CHECK-NEXT: 1 3 0.50 * ldrh.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1, #1]!
+# CHECK-NEXT: 1 2 0.50 * ldrh.w r0, [pc, #4]
+# CHECK-NEXT: 1 3 0.50 * ldrh r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrh.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U ldrht r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrsb.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrsb r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * ldrsb r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * ldrsb r0, [r1, #1]!
+# CHECK-NEXT: 1 2 0.50 * ldrsb.w r0, [pc, #4]
+# CHECK-NEXT: 1 3 0.50 * ldrsb r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrsb.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrsb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U ldrsbt r0, [r1, #1]
+# CHECK-NEXT: 1 3 0.50 * ldrsh.w r0, [r1, #2]
+# CHECK-NEXT: 1 3 0.50 * ldrsh r0, [r1, #-1]
+# CHECK-NEXT: 1 3 0.50 * ldrsh r0, [r1], #1
+# CHECK-NEXT: 1 3 0.50 * ldrsh r0, [r1, #1]!
+# CHECK-NEXT: 1 2 0.50 * ldrsh.w r0, [pc, #4]
+# CHECK-NEXT: 1 3 0.50 * ldrsh r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrsh.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 0.50 * ldrsh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 0.50 U ldrsht r0, [r1, #1]
+# CHECK-NEXT: 1 2 0.50 U ldrt r0, [r1, #1]
+# CHECK-NEXT: 1 1 1.00 lsls r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 lsl.w r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 lsls.w r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 lsls r0, r1
+# CHECK-NEXT: 1 1 1.00 lsl.w r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 lsls.w r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 lsrs r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 lsr.w r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 lsrs.w r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 lsrs r0, r1
+# CHECK-NEXT: 1 1 1.00 lsr.w r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 lsrs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 mla r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 mls r0, r1, r2, r3
+# CHECK-NEXT: 1 1 0.50 movs r0, #1
+# CHECK-NEXT: 1 1 0.50 mov.w r0, #1
+# CHECK-NEXT: 1 1 0.50 movs.w r0, #1
+# CHECK-NEXT: 1 1 0.50 movw r0, #1
+# CHECK-NEXT: 1 1 0.50 mov r0, r1
+# CHECK-NEXT: 1 1 0.50 mov.w r0, r1
+# CHECK-NEXT: 1 1 0.50 movs.w r0, r1
+# CHECK-NEXT: 1 1 0.50 movt r0, #1
+# CHECK-NEXT: 1 3 0.50 U mrs r0, apsr
+# CHECK-NEXT: 1 3 0.50 U msr apsr_nzcvq, r0
+# CHECK-NEXT: 1 2 1.00 muls r1, r2, r1
+# CHECK-NEXT: 1 2 1.00 mul r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 mvn r0, #1
+# CHECK-NEXT: 1 1 0.50 mvns r0, #1
+# CHECK-NEXT: 1 1 0.50 mvns r0, r1
+# CHECK-NEXT: 1 1 0.50 mvn.w r0, r1
+# CHECK-NEXT: 1 1 0.50 mvns.w r0, r1
+# CHECK-NEXT: 1 2 1.00 mvn.w r0, r1, lsl #1
+# CHECK-NEXT: 1 2 1.00 mvns.w r0, r1, lsl #1
+# CHECK-NEXT: 1 3 0.50 * * U nop
+# CHECK-NEXT: 1 3 0.50 * * U nop.w
+# CHECK-NEXT: 1 1 0.50 orn r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 orns r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 orn r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 orns r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 orn r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 orns r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 0.50 orr r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 orrs r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 orrs r0, r1
+# CHECK-NEXT: 1 1 0.50 orr.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 orrs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 orr.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 orrs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 pkhbt r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 pkhbt r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 pkhbt r0, r2, r1
+# CHECK-NEXT: 1 2 1.00 pkhtb r0, r1, r2, asr #1
+# CHECK-NEXT: 1 2 0.50 * U pop {r0}
+# CHECK-NEXT: 1 2 0.50 * pop.w {r0, r1}
+# CHECK-NEXT: 1 2 0.50 * ldr r0, [sp], #4
+# CHECK-NEXT: 1 3 1.00 * U push {r0}
+# CHECK-NEXT: 1 3 1.00 * push.w {r0, r1}
+# CHECK-NEXT: 1 3 1.00 * str r0, [sp, #-4]!
+# CHECK-NEXT: 1 2 1.00 qadd r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qadd16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qadd8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qasx r0, r1, r2
+# CHECK-NEXT: 1 3 1.00 qdadd r0, r1, r2
+# CHECK-NEXT: 1 3 1.00 qdsub r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qsax r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qsub r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qsub16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 qsub8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 rbit r0, r1
+# CHECK-NEXT: 1 1 1.00 rev r0, r1
+# CHECK-NEXT: 1 1 1.00 rev.w r0, r1
+# CHECK-NEXT: 1 1 1.00 rev16 r0, r1
+# CHECK-NEXT: 1 1 1.00 rev16.w r0, r1
+# CHECK-NEXT: 1 1 1.00 revsh r0, r1
+# CHECK-NEXT: 1 1 1.00 revsh.w r0, r1
+# CHECK-NEXT: 1 1 1.00 ror.w r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 rors.w r0, r1, #1
+# CHECK-NEXT: 1 1 1.00 rors r0, r1
+# CHECK-NEXT: 1 1 1.00 ror.w r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 rors.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 rrx r0, r1
+# CHECK-NEXT: 1 2 1.00 rrxs r0, r1
+# CHECK-NEXT: 1 1 0.50 rsbs r0, r1, #0
+# CHECK-NEXT: 1 1 0.50 rsb.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 rsbs.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 U rsb r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 U rsbs r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 rsb r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 rsbs r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 1.00 * * U sadd16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U sadd8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U sasx r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 sbc r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 sbcs r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 U sbcs r0, r1
+# CHECK-NEXT: 1 1 0.50 sbc.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 sbcs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sbc.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 sbcs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 sbfx r0, r1, #1, #2
+# CHECK-NEXT: 2 7 1.00 sdiv r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * sel r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shadd16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shadd8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shasx r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shsax r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shsub16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 shsub8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smlabb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlabt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlatb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlatt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlad r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smladx r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlal r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlalbb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlalbt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlaltb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlaltt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlald r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlaldx r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlawb r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlawt r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlsd r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlsdx r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlsld r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smlsldx r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smmla r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smmlar r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 U smmls r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smmlsr r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smmul r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smmulr r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smuad r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smuadx r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smulbb r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smulbt r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smultb r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smultt r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smull r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 smulwb r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smulwt r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smusd r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 smusdx r0, r1, r2
+# CHECK-NEXT: 1 3 1.00 ssat r0, #1, r2
+# CHECK-NEXT: 1 3 1.00 ssat r0, #1, r2, lsl #1
+# CHECK-NEXT: 1 3 1.00 ssat16 r0, #1, r1
+# CHECK-NEXT: 1 1 1.00 * * U ssax r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U ssub16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U ssub8 r0, r1, r2
+# CHECK-NEXT: 1 3 1.00 * stm r0!, {r1}
+# CHECK-NEXT: 1 3 1.00 * stm.w r0, {r1}
+# CHECK-NEXT: 1 3 1.00 * stm.w r0!, {r1}
+# CHECK-NEXT: 1 3 1.00 * stmdb r0, {r1}
+# CHECK-NEXT: 1 3 1.00 * str r1, [r0, #-4]!
+# CHECK-NEXT: 1 3 1.00 * str r0, [r1]
+# CHECK-NEXT: 1 3 1.00 * str r0, [r1, #4]
+# CHECK-NEXT: 1 3 1.00 * str r0, [sp, #4]
+# CHECK-NEXT: 1 3 1.00 * str.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 1.00 * str r0, [r1, #-1]
+# CHECK-NEXT: 1 3 1.00 * str r0, [r1], #1
+# CHECK-NEXT: 1 3 1.00 * str r0, [r1, r2]
+# CHECK-NEXT: 1 3 1.00 * str.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 1.00 * str.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 1.00 * strb r0, [r1]
+# CHECK-NEXT: 1 3 1.00 * strb r0, [r1, #1]
+# CHECK-NEXT: 1 3 1.00 * strb.w r0, [r1, #1]
+# CHECK-NEXT: 1 3 1.00 * strb r0, [r1, #-1]
+# CHECK-NEXT: 1 3 1.00 * strb r0, [r1], #1
+# CHECK-NEXT: 1 3 1.00 * strb r0, [r1, #1]!
+# CHECK-NEXT: 1 3 1.00 * strb r0, [r1, r2]
+# CHECK-NEXT: 1 3 1.00 * strb.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 1.00 * strb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 1.00 U strbt r0, [r1, #1]
+# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2, #4]
+# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2], #4
+# CHECK-NEXT: 1 3 1.00 * strd r0, r1, [r2, #4]!
+# CHECK-NEXT: 1 3 1.00 * * U strex r0, r1, [r2]
+# CHECK-NEXT: 1 3 1.00 * * U strex r0, r1, [r2, #4]
+# CHECK-NEXT: 1 3 1.00 * * U strexb r0, r1, [r2]
+# CHECK-NEXT: 1 3 1.00 * * U strexh r0, r1, [r2]
+# CHECK-NEXT: 1 3 1.00 * strh r0, [r1]
+# CHECK-NEXT: 1 3 1.00 * strh r0, [r1, #2]
+# CHECK-NEXT: 1 3 1.00 * strh.w r0, [r1, #2]
+# CHECK-NEXT: 1 3 1.00 * strh r0, [r1, #-1]
+# CHECK-NEXT: 1 3 1.00 * strh r0, [r1], #1
+# CHECK-NEXT: 1 3 1.00 * strh r0, [r1, #1]!
+# CHECK-NEXT: 1 3 1.00 * strh r0, [r1, r2]
+# CHECK-NEXT: 1 3 1.00 * strh.w r0, [r1, r2]
+# CHECK-NEXT: 1 3 1.00 * strh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: 1 3 1.00 U strht r0, [r1, #1]
+# CHECK-NEXT: 1 3 1.00 U strt r0, [r1, #1]
+# CHECK-NEXT: 1 1 0.50 subs r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 subs r0, #1
+# CHECK-NEXT: 1 1 0.50 sub.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 subs.w r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 subw r0, r1, #1
+# CHECK-NEXT: 1 1 0.50 subs r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 sub.w r0, r1, r2
+# CHECK-NEXT: 1 1 0.50 subs.w r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sub.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 2 1.00 subs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 1 1 0.50 U sub sp, #4
+# CHECK-NEXT: 1 1 0.50 sub.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 subs.w r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 subw r0, sp, #1
+# CHECK-NEXT: 1 1 0.50 sub.w r0, sp, r1
+# CHECK-NEXT: 1 1 0.50 subs.w r0, sp, r1
+# CHECK-NEXT: 1 2 1.00 sub.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 1 2 1.00 subs.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 1 2 1.00 sxtab r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sxtab r0, r1, r2, ror #8
+# CHECK-NEXT: 1 2 1.00 sxtab16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sxtab16 r0, r1, r2, ror #8
+# CHECK-NEXT: 1 2 1.00 sxtah r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 sxtah r0, r1, r2, ror #8
+# CHECK-NEXT: 1 1 1.00 sxtb r0, r1
+# CHECK-NEXT: 1 1 1.00 sxtb.w r0, r1
+# CHECK-NEXT: 1 1 1.00 sxtb.w r0, r1, ror #8
+# CHECK-NEXT: 1 1 1.00 sxtb16 r0, r1
+# CHECK-NEXT: 1 1 1.00 sxtb16 r0, r1, ror #8
+# CHECK-NEXT: 1 1 1.00 sxth r0, r1
+# CHECK-NEXT: 1 1 1.00 sxth.w r0, r1
+# CHECK-NEXT: 1 1 1.00 sxth.w r0, r1, ror #8
+# CHECK-NEXT: 2 2 0.50 U tbb [r0, r1]
+# CHECK-NEXT: 2 2 0.50 U tbh [r0, r1, lsl #1]
+# CHECK-NEXT: 1 1 0.50 teq.w r0, #1
+# CHECK-NEXT: 1 1 0.50 teq.w r0, r1
+# CHECK-NEXT: 1 2 1.00 teq.w r0, r1, lsl #1
+# CHECK-NEXT: 1 1 0.50 tst.w r0, #1
+# CHECK-NEXT: 1 1 0.50 tst r0, r1
+# CHECK-NEXT: 1 1 0.50 tst.w r0, r1
+# CHECK-NEXT: 1 2 1.00 tst.w r0, r1, lsl #1
+# CHECK-NEXT: 1 1 1.00 * * U uadd16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U uadd8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U uasx r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 ubfx r0, r1, #1, #2
+# CHECK-NEXT: 2 7 1.00 udiv r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhadd16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhadd8 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhasx r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhsax r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhsub16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 uhsub8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 umaal r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 umlal r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 umull r0, r1, r2, r3
+# CHECK-NEXT: 1 2 1.00 uqadd16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqadd8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqasx r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqsax r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqsub16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uqsub8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 usad8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 usada8 r0, r1, r2, r3
+# CHECK-NEXT: 1 3 1.00 usat r0, #1, r1
+# CHECK-NEXT: 1 3 1.00 usat r0, #1, r1, lsl #1
+# CHECK-NEXT: 1 3 1.00 usat16 r0, #1, r1
+# CHECK-NEXT: 1 1 1.00 * * U usax r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U usub16 r0, r1, r2
+# CHECK-NEXT: 1 1 1.00 * * U usub8 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uxtab r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uxtab r0, r1, r2, ror #8
+# CHECK-NEXT: 1 2 1.00 uxtab16 r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uxtab16 r0, r1, r2, ror #8
+# CHECK-NEXT: 1 2 1.00 uxtah r0, r1, r2
+# CHECK-NEXT: 1 2 1.00 uxtah r0, r1, r2, ror #8
+# CHECK-NEXT: 1 1 1.00 uxtb r0, r1
+# CHECK-NEXT: 1 1 1.00 uxtb.w r0, r1
+# CHECK-NEXT: 1 1 1.00 uxtb.w r0, r1, ror #8
+# CHECK-NEXT: 1 1 1.00 uxtb16 r0, r1
+# CHECK-NEXT: 1 1 1.00 uxtb16 r0, r1, ror #8
+# CHECK-NEXT: 1 1 1.00 uxth r0, r1
+# CHECK-NEXT: 1 1 1.00 uxth.w r0, r1
+# CHECK-NEXT: 1 1 1.00 uxth.w r0, r1, ror #8
+# CHECK-NEXT: 1 3 0.50 * * U wfe
+# CHECK-NEXT: 1 3 0.50 * * U wfi
+# CHECK-NEXT: 1 3 0.50 * * U yield
+
+# CHECK: Resources:
+# CHECK-NEXT: [0.0] - M7UnitALU
+# CHECK-NEXT: [0.1] - M7UnitALU
+# CHECK-NEXT: [1] - M7UnitBranch
+# CHECK-NEXT: [2.0] - M7UnitLoad
+# CHECK-NEXT: [2.1] - M7UnitLoad
+# CHECK-NEXT: [3] - M7UnitMAC
+# CHECK-NEXT: [4] - M7UnitSIMD
+# CHECK-NEXT: [5] - M7UnitShift1
+# CHECK-NEXT: [6] - M7UnitShift2
+# CHECK-NEXT: [7] - M7UnitStore
+# CHECK-NEXT: [8] - M7UnitVFP
+# CHECK-NEXT: [9.0] - M7UnitVPort
+# CHECK-NEXT: [9.1] - M7UnitVPort
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1]
+# CHECK-NEXT: 125.00 125.00 - 35.00 35.00 43.00 90.00 88.00 2.00 45.00 - - -
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0.0] [0.1] [1] [2.0] [2.1] [3] [4] [5] [6] [7] [8] [9.0] [9.1] Instructions:
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adc r0, r1, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adcs r0, r1, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adcs r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adc.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adcs.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - adc.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - adcs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adds r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adds r0, #42
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - add.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adds.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - addw r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adds r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - add r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - add.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adds.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - add.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - adds.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - add.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - add.w sp, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - add.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adds.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - addw r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - add r0, sp, r0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - add sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - add.w r0, sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adds.w r0, sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - add.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - adds.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - adr.w r0, #-6
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - and r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - ands r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - ands r1, r0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - and.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - ands.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - and.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - ands.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - asrs r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - asr.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - asrs.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - asrs r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - asr.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - asrs.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - bfc r0, #1, #2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - bfi r0, r1, #1, #2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - bic r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - bics r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - bics r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - bic.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - bics.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - bic.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - bics.w r0, r1, r2, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - bkpt #1
+# CHECK-NEXT: - - - - - - - - - - - - - clrex
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - clz r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmn.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmn r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmn.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - cmn.w r0, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmp r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmp.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmp r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmp r0, r10
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - cmp.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - cmp.w r0, r1, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - dmb sy
+# CHECK-NEXT: - - - - - - - - - - - - - dsb sy
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - eor r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - eors r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - eors r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - eor.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - eors.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - eor.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - eors.w r0, r1, r2, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - isb sy
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldm r0!, {r1}
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldm.w r0, {r1}
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldm.w r0, {r1}
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr r1, [r0], #4
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldmdb r0, {r1}
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldmdb r0!, {r1}
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr r0, [r1, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr r0, [sp, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr.w r0, [r1, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr r0, [r1, #-1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr r0, [r1], #1
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr r0, [r1, #1]!
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr r0, [pc, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr.w r0, [pc, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr.w r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrb r0, [r1, #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrb.w r0, [r1, #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrb r0, [r1, #-1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrb r0, [r1], #1
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrb r0, [r1, #1]!
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrb.w r0, [pc, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrb r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrb.w r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrbt r0, [r1, #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrd r0, r2, [r1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrd r0, r2, [r1, #-4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrd r0, r2, [r1], #4
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrd r0, r2, [r1, #4]!
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrd r0, r2, next
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrex r0, [r1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrex r0, [r1, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrexb r0, [r1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrexh r0, [r1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrh r0, [r1, #2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrh.w r0, [r1, #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrh r0, [r1, #-1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrh r0, [r1], #1
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrh r0, [r1, #1]!
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrh.w r0, [pc, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrh r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrh.w r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrht r0, [r1, #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsb.w r0, [r1, #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsb r0, [r1, #-1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsb r0, [r1], #1
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsb r0, [r1, #1]!
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsb.w r0, [pc, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsb r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsb.w r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsbt r0, [r1, #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsh.w r0, [r1, #2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsh r0, [r1, #-1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsh r0, [r1], #1
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsh r0, [r1, #1]!
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsh.w r0, [pc, #4]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsh r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsh.w r0, [r1, r2]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrsht r0, [r1, #1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldrt r0, [r1, #1]
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsls r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsl.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsls.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsls r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsl.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsls.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsrs r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsr.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsrs.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsrs r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsr.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - lsrs.w r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - mla r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - mls r0, r1, r2, r3
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - movs r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mov.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - movs.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - movw r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mov r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mov.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - movs.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - movt r0, #1
+# CHECK-NEXT: - - - - - - - - - - - - - mrs r0, apsr
+# CHECK-NEXT: - - - - - - - - - - - - - msr apsr_nzcvq, r0
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - muls r1, r2, r1
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - mul r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mvn r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mvns r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mvns r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mvn.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - mvns.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - mvn.w r0, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - mvns.w r0, r1, lsl #1
+# CHECK-NEXT: - - - - - - - - - - - - - nop
+# CHECK-NEXT: - - - - - - - - - - - - - nop.w
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - orn r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - orns r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - orn r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - orns r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - orn r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - orns r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - orr r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - orrs r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - orrs r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - orr.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - orrs.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - orr.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - orrs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - pkhbt r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - pkhbt r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - pkhbt r0, r2, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - pkhtb r0, r1, r2, asr #1
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - pop {r0}
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - pop.w {r0, r1}
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - ldr r0, [sp], #4
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - push {r0}
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - push.w {r0, r1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str r0, [sp, #-4]!
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - qadd r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - qadd16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - qadd8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - qasx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - qdadd r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - qdsub r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - qsax r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - qsub r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - qsub16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - qsub8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - rbit r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - rev r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - rev.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - rev16 r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - rev16.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - revsh r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - revsh.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - ror.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - rors.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - rors r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - ror.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - rors.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - - - rrx r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - 1.00 - - - - rrxs r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - rsbs r0, r1, #0
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - rsb.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - rsbs.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - rsb r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - rsbs r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - rsb r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - rsbs r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sadd16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sadd8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sasx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sbc r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sbcs r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sbcs r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sbc.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sbcs.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - sbc.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - sbcs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - sbfx r0, r1, #1, #2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - sdiv r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sel r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - shadd16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - shadd8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - shasx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - shsax r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - shsub16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - shsub8 r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlabb r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlabt r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlatb r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlatt r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlad r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smladx r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlal r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlalbb r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlalbt r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlaltb r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlaltt r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlald r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlaldx r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlawb r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlawt r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlsd r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlsdx r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlsld r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smlsldx r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smmla r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smmlar r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smmls r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smmlsr r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smmul r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smmulr r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smuad r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smuadx r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smulbb r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smulbt r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smultb r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smultt r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smull r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smulwb r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smulwt r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smusd r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - smusdx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - ssat r0, #1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - ssat r0, #1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - ssat16 r0, #1, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - ssax r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - ssub16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - ssub8 r0, r1, r2
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - stm r0!, {r1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - stm.w r0, {r1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - stm.w r0!, {r1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - stmdb r0, {r1}
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str r1, [r0, #-4]!
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str r0, [r1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str r0, [r1, #4]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str r0, [sp, #4]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str.w r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str r0, [r1, #-1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str r0, [r1], #1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - str.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strb r0, [r1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strb r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strb.w r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strb r0, [r1, #-1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strb r0, [r1], #1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strb r0, [r1, #1]!
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strb r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strb.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strb.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strbt r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strd r0, r1, [r2, #4]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strd r0, r1, [r2], #4
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strd r0, r1, [r2, #4]!
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strex r0, r1, [r2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strex r0, r1, [r2, #4]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strexb r0, r1, [r2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strexh r0, r1, [r2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strh r0, [r1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strh r0, [r1, #2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strh.w r0, [r1, #2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strh r0, [r1, #-1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strh r0, [r1], #1
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strh r0, [r1, #1]!
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strh r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strh.w r0, [r1, r2]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strh.w r0, [r1, r2, lsl #1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strht r0, [r1, #1]
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - strt r0, [r1, #1]
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - subs r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - subs r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sub.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - subs.w r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - subw r0, r1, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - subs r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sub.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - subs.w r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - sub.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - subs.w r0, r1, r2, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sub sp, #4
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sub.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - subs.w r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - subw r0, sp, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - sub.w r0, sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - subs.w r0, sp, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - sub.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - subs.w r0, sp, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - sxtab r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - sxtab r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - sxtab16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - sxtab16 r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - sxtah r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - sxtah r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sxtb r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sxtb.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sxtb.w r0, r1, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sxtb16 r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sxtb16 r0, r1, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sxth r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sxth.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - sxth.w r0, r1, ror #8
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - tbb [r0, r1]
+# CHECK-NEXT: - - - 0.50 0.50 - - - - - - - - tbh [r0, r1, lsl #1]
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - teq.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - teq.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - teq.w r0, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - tst.w r0, #1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - tst r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - - tst.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - - 1.00 - - - - - tst.w r0, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uadd16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uadd8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uasx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - ubfx r0, r1, #1, #2
+# CHECK-NEXT: 1.00 1.00 - - - - - - - - - - - udiv r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uhadd16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uhadd8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uhasx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uhsax r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uhsub16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uhsub8 r0, r1, r2
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - umaal r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - umlal r0, r1, r2, r3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - umull r0, r1, r2, r3
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uqadd16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uqadd8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uqasx r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uqsax r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uqsub16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uqsub8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - usad8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - usada8 r0, r1, r2, r3
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - usat r0, #1, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - usat r0, #1, r1, lsl #1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - usat16 r0, #1, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - usax r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - usub16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - usub8 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - uxtab r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - uxtab r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - uxtab16 r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - uxtab16 r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - uxtah r0, r1, r2
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 1.00 - - - - - uxtah r0, r1, r2, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uxtb r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uxtb.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uxtb.w r0, r1, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uxtb16 r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uxtb16 r0, r1, ror #8
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uxth r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uxth.w r0, r1
+# CHECK-NEXT: 0.50 0.50 - - - - 1.00 - - - - - - uxth.w r0, r1, ror #8
+# CHECK-NEXT: - - - - - - - - - - - - - wfe
+# CHECK-NEXT: - - - - - - - - - - - - - wfi
+# CHECK-NEXT: - - - - - - - - - - - - - yield
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