[PATCH] D91518: [LV][NFC-ish] Allow vector widths over 256 elements

[Simon Moll via Phabricator via llvm-commits]

simoll created this revision.
simoll added reviewers: fhahn, k-ishizaka, kaz7.
Herald added subscribers: llvm-commits, hiraditya.
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The assertion that vector widths are <= 256 elements was hard wired in the LV code. Remove that  - this is an NFC for non-asserting builds.
Eg, VE allows for vectors up to 512 elements.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91518

Files:
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp


Index: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
===================================================================
--- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5349,8 +5349,6 @@
   LLVM_DEBUG(dbgs() << "LV: The Widest register safe to use is: "
                     << WidestRegister << " bits.\n");
 
-  assert(MaxVectorSize <= 256 && "Did not expect to pack so many elements"
-                                 " into one vector!");
   if (MaxVectorSize == 0) {
     LLVM_DEBUG(dbgs() << "LV: The target has no vector registers.\n");
     MaxVectorSize = 1;


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