[PATCH] D82227: SLP: honor requested max vector size merging PHIs

Fri Nov 13 15:42:41 PST 2020

vdmitrie added a comment.

In D82227#2389212 <https://reviews.llvm.org/D82227#2389212>, @jonpa wrote:

> I am afraid that this patch actually has a bad impact on performance on SystemZ, and unfortunately this was not known until now. It would be very appreciated if we could rework this and get back the old behaviour on SystemZ somehow...
>
> See https://bugs.llvm.org/show_bug.cgi?id=48155

We also observed regression on x86 for imagick after this patch. I'm not sure whether we observed the same case but it was definitely related to this patch.
Here is what happened:
SLP vectorizer started from 5 PHIs of i64 type. And it turned out unfortunate to have only the last four of them being perfectly vectorizable with VF=4.
Max register size blindly cut that list taking the first four of them that were unprofitable to vectorize and thus left the good one even outside of possible try out window. SLP finally end up vectorizing just two of them with VF=2.
Before the patch the vectorizer after failed attempt to vectorize first four scalars took the next four (last in the list) and succeeded.
Assuming max vector size is power of two it probably makes sense to cut list at 2*MaxRegSize-1 rather than at MaxRegSize.

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