[PATCH] D91487: [AMDGPU] Don't require swz operand for non-return Atomics.

[Matthew Dawson via Phabricator via llvm-commits]

MJDSys created this revision.
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When legalizing operands for instructions that are not atmoics with
a return, do not assume the swz operand is present.

This avoids an assert in the openmm test suite.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91487

Files:
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp


Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5244,7 +5244,10 @@
           MIB.addImm(TFE->getImm());
         }
 
-        MIB.addImm(getNamedImmOperand(MI, AMDGPU::OpName::swz));
+        if (const MachineOperand *SWZ =
+                getNamedOperand(MI, AMDGPU::OpName::swz)) {
+          MIB.addImm(SWZ->getImm());
+        }
 
         MIB.cloneMemRefs(MI);
         Addr64 = MIB;
@@ -5289,6 +5292,7 @@
 
   while (!Worklist.empty()) {
     MachineInstr &Inst = *Worklist.pop_back_val();
+    LLVM_DEBUG(dbgs() << "Moving to VALU " << Inst);
     MachineBasicBlock *MBB = Inst.getParent();
     MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
 


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