[llvm] 835c462 - [RISCV] Add test case showing failure to use GREVIW for i32 bitreverse if result is not sign extended. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 13 12:42:00 PST 2020
Author: Craig Topper
Date: 2020-11-13T12:41:41-08:00
New Revision: 835c462eae739cf09877597f0c7da43b8aac4bdf
URL: https://github.com/llvm/llvm-project/commit/835c462eae739cf09877597f0c7da43b8aac4bdf
DIFF: https://github.com/llvm/llvm-project/commit/835c462eae739cf09877597f0c7da43b8aac4bdf.diff
LOG: [RISCV] Add test case showing failure to use GREVIW for i32 bitreverse if result is not sign extended. NFC
Added:
Modified:
llvm/test/CodeGen/RISCV/rv64Zbp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/rv64Zbp.ll b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
index 3c8aa65909b2..95fde9fb2cf2 100644
--- a/llvm/test/CodeGen/RISCV/rv64Zbp.ll
+++ b/llvm/test/CodeGen/RISCV/rv64Zbp.ll
@@ -1126,6 +1126,115 @@ define signext i32 @bitreverse_i32(i32 signext %a) nounwind {
ret i32 %1
}
+; Similar to bitreverse_i32 but the result is not sign extended.
+; FIXME: We should use greviw here.
+define void @bitreverse_i32_nosext(i32 signext %a, i32* %x) nounwind {
+; RV64I-LABEL: bitreverse_i32_nosext:
+; RV64I: # %bb.0:
+; RV64I-NEXT: srli a2, a0, 24
+; RV64I-NEXT: lui a3, 4080
+; RV64I-NEXT: and a2, a2, a3
+; RV64I-NEXT: srli a3, a0, 8
+; RV64I-NEXT: addi a4, zero, 255
+; RV64I-NEXT: slli a5, a4, 24
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: or a2, a3, a2
+; RV64I-NEXT: srli a3, a0, 40
+; RV64I-NEXT: lui a5, 16
+; RV64I-NEXT: addiw a5, a5, -256
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: srli a5, a0, 56
+; RV64I-NEXT: or a3, a3, a5
+; RV64I-NEXT: or a6, a2, a3
+; RV64I-NEXT: slli a3, a0, 8
+; RV64I-NEXT: slli a5, a4, 32
+; RV64I-NEXT: and a3, a3, a5
+; RV64I-NEXT: slli a5, a0, 24
+; RV64I-NEXT: slli a2, a4, 40
+; RV64I-NEXT: and a2, a5, a2
+; RV64I-NEXT: or a2, a2, a3
+; RV64I-NEXT: slli a3, a0, 40
+; RV64I-NEXT: slli a4, a4, 48
+; RV64I-NEXT: and a3, a3, a4
+; RV64I-NEXT: slli a0, a0, 56
+; RV64I-NEXT: or a0, a0, a3
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: or a0, a0, a6
+; RV64I-NEXT: lui a2, 3855
+; RV64I-NEXT: addiw a2, a2, 241
+; RV64I-NEXT: slli a2, a2, 12
+; RV64I-NEXT: addi a2, a2, -241
+; RV64I-NEXT: slli a2, a2, 12
+; RV64I-NEXT: addi a2, a2, 241
+; RV64I-NEXT: slli a2, a2, 12
+; RV64I-NEXT: addi a2, a2, -241
+; RV64I-NEXT: and a2, a0, a2
+; RV64I-NEXT: slli a2, a2, 4
+; RV64I-NEXT: lui a3, 1044721
+; RV64I-NEXT: addiw a3, a3, -241
+; RV64I-NEXT: slli a3, a3, 12
+; RV64I-NEXT: addi a3, a3, 241
+; RV64I-NEXT: slli a3, a3, 12
+; RV64I-NEXT: addi a3, a3, -241
+; RV64I-NEXT: slli a3, a3, 12
+; RV64I-NEXT: addi a3, a3, 240
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: srli a0, a0, 4
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: lui a2, 13107
+; RV64I-NEXT: addiw a2, a2, 819
+; RV64I-NEXT: slli a2, a2, 12
+; RV64I-NEXT: addi a2, a2, 819
+; RV64I-NEXT: slli a2, a2, 12
+; RV64I-NEXT: addi a2, a2, 819
+; RV64I-NEXT: slli a2, a2, 12
+; RV64I-NEXT: addi a2, a2, 819
+; RV64I-NEXT: and a2, a0, a2
+; RV64I-NEXT: slli a2, a2, 2
+; RV64I-NEXT: lui a3, 1035469
+; RV64I-NEXT: addiw a3, a3, -819
+; RV64I-NEXT: slli a3, a3, 12
+; RV64I-NEXT: addi a3, a3, -819
+; RV64I-NEXT: slli a3, a3, 12
+; RV64I-NEXT: addi a3, a3, -819
+; RV64I-NEXT: slli a3, a3, 12
+; RV64I-NEXT: addi a3, a3, -820
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: srli a0, a0, 2
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: lui a2, 349525
+; RV64I-NEXT: addiw a2, a2, 1365
+; RV64I-NEXT: slli a2, a2, 32
+; RV64I-NEXT: and a2, a0, a2
+; RV64I-NEXT: slli a2, a2, 1
+; RV64I-NEXT: lui a3, 873813
+; RV64I-NEXT: addiw a3, a3, 1365
+; RV64I-NEXT: slli a3, a3, 33
+; RV64I-NEXT: and a0, a0, a3
+; RV64I-NEXT: srli a0, a0, 1
+; RV64I-NEXT: or a0, a0, a2
+; RV64I-NEXT: srli a0, a0, 32
+; RV64I-NEXT: sw a0, 0(a1)
+; RV64I-NEXT: ret
+;
+; RV64IB-LABEL: bitreverse_i32_nosext:
+; RV64IB: # %bb.0:
+; RV64IB-NEXT: rev a0, a0
+; RV64IB-NEXT: srli a0, a0, 32
+; RV64IB-NEXT: sw a0, 0(a1)
+; RV64IB-NEXT: ret
+;
+; RV64IBP-LABEL: bitreverse_i32_nosext:
+; RV64IBP: # %bb.0:
+; RV64IBP-NEXT: rev a0, a0
+; RV64IBP-NEXT: srli a0, a0, 32
+; RV64IBP-NEXT: sw a0, 0(a1)
+; RV64IBP-NEXT: ret
+ %1 = tail call i32 @llvm.bitreverse.i32(i32 %a)
+ store i32 %1, i32* %x
+ ret void
+}
+
declare i64 @llvm.bitreverse.i64(i64)
define i64 @bitreverse_i64(i64 %a) nounwind {
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