[PATCH] D91449: [RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb.

[Craig Topper via Phabricator via llvm-commits]

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This should result in better utilization of ROLW/RORW since we
don't need to look for a SIGN_EXTEND_INREG that may not exist.

      

Also remove rotl/rotr isel matching to GREVI and just prefer RORI.
This is to keep consistency so we don't have to match ROLW/RORW
to GREVIW as well. I imagine RORI/RORIW performance will be the
same or better than GREVI.


https://reviews.llvm.org/D91449

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoB.td
  llvm/test/CodeGen/RISCV/rv32Zbp.ll
  llvm/test/CodeGen/RISCV/rv64Zbbp.ll
  llvm/test/CodeGen/RISCV/rv64Zbp.ll

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