[PATCH] D91259: [RISCV] Lower GREVI and GORCI as custom nodes
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 13 08:16:41 PST 2020
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1153
+// Match the following pattern as a GORCI(W) operation
+// (or (or (BITMANIP_SHL x), x),
+// (BITMANIP_SRL x))
----------------
frasercrmck wrote:
> craig.topper wrote:
> > Is it possible that the input is (or (or (BITMANIP_SHL x), (BITMANIP_SHR x)), x)?
> Yeah. It's currently generating this on RV32 master:
>
> ```
> %shl = shl i32 %a, 16
> %shr = lshr i32 %a, 16
> %or = or i32 %shr, %shl
> %or2 = or i32 %or, %a
> ret i32 %or2
>
> -->
> rev16 a1, a0
> or a0, a1, a0
> ```
>
> In that case it's essentially `or (grevi x), x)` so could in theory be picked up like that rather than fully exploring all potential combinations of `(or (or x, y), (or z, w))` inputs.
>
> Sadly though LLVM is picking up that `shl/srl` as `rotl`, and still being TableGen pattern matched to grev.
>
> That relates to my other comment, that we might need to dive further into `rotl`, `rotr`, `bswap` and `bitreverse` to find more opportunities.
Can you post your patch to a separate review? I'd like to experiment with it.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D91259/new/
https://reviews.llvm.org/D91259
More information about the llvm-commits
mailing list