[PATCH] D91420: [PowerPC][PCRelative] Add new seudo instructions for PCRel TLS to fix R2 clobber issue

[Victor Huang via Phabricator via llvm-commits]

NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, bsaleil, amyk, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: llvm-commits, shchenz, kbarton, hiraditya.
NeHuang requested review of this revision.

New seudo instructions `GETtlsADDRPCREL` and `GETtlsldADDRPCREL` are added for properly setting REGMASK for `tls_get_addr` function when using PCRelative address.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91420

Files:
  llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
  llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll


Index: llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/pcrel-tls_get_addr_clobbers.ll
@@ -0,0 +1,25 @@
+; RUN: llc -verify-machineinstrs -mtriple="powerpc64le-unknown-linux-gnu" \
+; RUN:  -ppc-asm-full-reg-names -mcpu=pwr10 -relocation-model=pic < %s | FileCheck %s
+
+%0 = type { i32 (...)**, %0* }
+ at x = external dso_local thread_local unnamed_addr global %0*, align 8
+define void @test(i8* %arg) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    mflr r0
+; CHECK:         std r30, -16(r1)
+; CHECK-NEXT:    std r0, 16(r1)
+; CHECK-NEXT:    stdu r1, -48(r1)
+; CHECK-NEXT:    mr r30, r3
+; CHECK-NEXT:    paddi r3, 0, x at got@tlsld at pcrel, 1
+; CHECK-NEXT:    bl __tls_get_addr at notoc(x at tlsld)
+; CHECK-NEXT:    paddi r3, r3, x at DTPREL, 0
+; CHECK-NEXT:    std r30, 0(r3)
+; CHECK-NEXT:    addi r1, r1, 48
+; CHECK-NEXT:    ld r0, 16(r1)
+; CHECK-NEXT:    ld r30, -16(r1)
+; CHECK-NEXT:    mtlr r0
+entry:
+  store i8* %arg, i8** bitcast (%0** @x to i8**), align 8
+  ret void
+}
Index: llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
+++ llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp
@@ -111,8 +111,8 @@
           Opc1 = PPC::PADDI8pc;
           Opc2 = MI.getOperand(2).getTargetFlags() ==
                          PPCII::MO_GOT_TLSGD_PCREL_FLAG
-                     ? PPC::GETtlsADDR
-                     : PPC::GETtlsldADDR;
+                     ? PPC::GETtlsADDRPCREL
+                     : PPC::GETtlsldADDRPCREL;
         }
 
         // We create ADJCALLSTACKUP and ADJCALLSTACKDOWN around _tls_get_addr
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1276,6 +1276,14 @@
                         [(set i64:$rD,
                           (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
                  isPPC64;
+
+let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1, Size = 8,
+    Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
+def GETtlsADDRPCREL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
+                             "#GETtlsADDRPCREL",
+                             [(set i64:$rD,
+                               (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
+                      isPPC64;
 // Combined op for ADDItlsgdL and GETtlsADDR, late expanded.  X3 and LR8
 // are true defines while the rest of the Defs are clobbers.
 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
@@ -1308,6 +1316,14 @@
                           [(set i64:$rD,
                             (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
                    isPPC64;
+
+let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
+    Defs = [X0,X2,X4,X5,X6,X7,X8,X9,X10,X11,X12,LR8,CTR8,CR0,CR1,CR5,CR6,CR7] in
+def GETtlsldADDRPCREL : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
+                               "#GETtlsldADDRPCREL",
+                               [(set i64:$rD,
+                                 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
+                        isPPC64;
 // Combined op for ADDItlsldL and GETtlsADDR, late expanded.  X3 and LR8
 // are true defines, while the rest of the Defs are clobbers.
 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -1076,6 +1076,7 @@
   case PPC::GETtlsADDR:
     // Transform: %x3 = GETtlsADDR %x3, @sym
     // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsgd)
+  case PPC::GETtlsADDRPCREL:
   case PPC::GETtlsADDR32: {
     // Transform: %r3 = GETtlsADDR32 %r3, @sym
     // Into: BL_TLS __tls_get_addr(sym at tlsgd)@PLT
@@ -1121,6 +1122,7 @@
   case PPC::GETtlsldADDR:
     // Transform: %x3 = GETtlsldADDR %x3, @sym
     // Into: BL8_NOP_TLS __tls_get_addr(sym at tlsld)
+  case PPC::GETtlsldADDRPCREL:
   case PPC::GETtlsldADDR32: {
     // Transform: %r3 = GETtlsldADDR32 %r3, @sym
     // Into: BL_TLS __tls_get_addr(sym at tlsld)@PLT


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