[PATCH] D91416: [VE] LVLGen sets VL before vector insts

[Simon Moll via Phabricator via llvm-commits]

simoll created this revision.
simoll added reviewers: kaz7, k-ishizaka.
simoll added a project: VE.
Herald added subscribers: llvm-commits, hiraditya, mgorny.
Herald added a project: LLVM.
simoll requested review of this revision.

The VE backend represents vector instructions with an explicit 'i32'
vector length operand.  In the VE ISA, the vector length is always read
from the VL hardware register.  The LVLGen pass inserts 'lvl'
instructions as necessary to set VL to the right value before each
vector instruction.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91416

Files:
  llvm/lib/Target/VE/CMakeLists.txt
  llvm/lib/Target/VE/LVLGen.cpp
  llvm/lib/Target/VE/VE.h
  llvm/lib/Target/VE/VETargetMachine.cpp
  llvm/test/CodeGen/VE/VELIntrinsics/lvlgen.ll
  llvm/test/CodeGen/VE/VELIntrinsics/vld.ll
  llvm/test/CodeGen/VE/VELIntrinsics/vst.ll

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