[llvm] 7da0d0a - [MC][mips] Remove unused check prefixes. NFC
Simon Atanasyan via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 13 03:31:37 PST 2020
Author: Simon Atanasyan
Date: 2020-11-13T14:31:13+03:00
New Revision: 7da0d0a67ffc61a455512103f00a53a27d880bdc
URL: https://github.com/llvm/llvm-project/commit/7da0d0a67ffc61a455512103f00a53a27d880bdc
DIFF: https://github.com/llvm/llvm-project/commit/7da0d0a67ffc61a455512103f00a53a27d880bdc.diff
LOG: [MC][mips] Remove unused check prefixes. NFC
Added:
Modified:
llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll
llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll
llvm/test/CodeGen/Mips/cconv/arguments-float.ll
llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
llvm/test/CodeGen/Mips/cconv/vector.ll
llvm/test/CodeGen/Mips/ehframe-indirect.ll
llvm/test/CodeGen/Mips/fmadd1.ll
llvm/test/CodeGen/Mips/fpbr.ll
llvm/test/CodeGen/Mips/llvm-ir/mul.ll
llvm/test/CodeGen/Mips/llvm-ir/ret.ll
llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
llvm/test/CodeGen/Mips/llvm-ir/sub.ll
llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
llvm/test/CodeGen/Mips/load-store-left-right.ll
llvm/test/CodeGen/Mips/madd-msub.ll
llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
llvm/test/CodeGen/Mips/mips64shift.ll
llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
llvm/test/CodeGen/Mips/msa/frameindex.ll
llvm/test/CodeGen/Mips/msa/i5-s.ll
llvm/test/CodeGen/Mips/reloc-jalr.ll
llvm/test/CodeGen/Mips/unalignedload.ll
llvm/test/MC/Mips/elf_header.s
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
index 1a2ad44b0a6b..8bf41e01a979 100644
--- a/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
@@ -1,9 +1,7 @@
; RUN: llc < %s -march=mipsel -mcpu=mips32 -O0 -relocation-model=pic \
-; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=32R1
+; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -O0 -relocation-model=pic \
-; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=32R2
+; RUN: -fast-isel-abort=3 -verify-machineinstrs | FileCheck %s
@str = private unnamed_addr constant [12 x i8] c"hello there\00", align 1
@src = global i8* getelementptr inbounds ([12 x i8], [12 x i8]* @str, i32 0, i32 0), align 4
@@ -15,38 +13,37 @@ declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly,
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1)
define void @cpy(i8* %src, i32 %i) {
- ; ALL-LABEL: cpy:
+ ; CHECK-LABEL: cpy:
- ; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
- ; ALL: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}})
- ; ALL: jalr $[[T2]]
- ; ALL-NEXT: nop
- ; ALL-NOT: {{.*}}$2{{.*}}
+ ; CHECK: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
+ ; CHECK: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}})
+ ; CHECK: jalr $[[T2]]
+ ; CHECK-NEXT: nop
+ ; CHECK-NOT: {{.*}}$2{{.*}}
call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), i8* %src, i32 %i, i1 false)
ret void
}
define void @mov(i8* %src, i32 %i) {
- ; ALL-LABEL: mov:
+ ; CHECK-LABEL: mov:
-
- ; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
- ; ALL: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}})
- ; ALL: jalr $[[T2]]
- ; ALL-NEXT: nop
- ; ALL-NOT: {{.*}}$2{{.*}}
+ ; CHECK: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
+ ; CHECK: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}})
+ ; CHECK: jalr $[[T2]]
+ ; CHECK-NEXT: nop
+ ; CHECK-NOT: {{.*}}$2{{.*}}
call void @llvm.memmove.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), i8* %src, i32 %i, i1 false)
ret void
}
define void @clear(i32 %i) {
- ; ALL-LABEL: clear:
+ ; CHECK-LABEL: clear:
- ; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
- ; ALL: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}})
- ; ALL: jalr $[[T2]]
- ; ALL-NEXT: nop
- ; ALL-NOT: {{.*}}$2{{.*}}
+ ; CHECK: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
+ ; CHECK: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}})
+ ; CHECK: jalr $[[T2]]
+ ; CHECK-NEXT: nop
+ ; CHECK-NOT: {{.*}}$2{{.*}}
call void @llvm.memset.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), i8 42, i32 %i, i1 false)
ret void
}
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll
index c3366430d617..87d642d655cf 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ceil_and_floor.ll
@@ -1,21 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
declare float @llvm.ceil.f32(float)
define float @ceil_f32(float %a) {
-; MIPS32-LABEL: ceil_f32:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $sp, $sp, -24
-; MIPS32-NEXT: .cfi_def_cfa_offset 24
-; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: .cfi_offset 31, -4
-; MIPS32-NEXT: jal ceilf
-; MIPS32-NEXT: nop
-; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MIPS32-NEXT: addiu $sp, $sp, 24
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ceil_f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $sp, $sp, -24
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset 31, -4
+; CHECK-NEXT: jal ceilf
+; CHECK-NEXT: nop
+; CHECK-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; CHECK-NEXT: addiu $sp, $sp, 24
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%0 = call float @llvm.ceil.f32(float %a)
ret float %0
@@ -23,18 +25,18 @@ entry:
declare double @llvm.ceil.f64(double)
define double @ceil_f64(double %a) {
-; MIPS32-LABEL: ceil_f64:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $sp, $sp, -24
-; MIPS32-NEXT: .cfi_def_cfa_offset 24
-; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: .cfi_offset 31, -4
-; MIPS32-NEXT: jal ceil
-; MIPS32-NEXT: nop
-; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MIPS32-NEXT: addiu $sp, $sp, 24
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ceil_f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $sp, $sp, -24
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset 31, -4
+; CHECK-NEXT: jal ceil
+; CHECK-NEXT: nop
+; CHECK-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; CHECK-NEXT: addiu $sp, $sp, 24
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%0 = call double @llvm.ceil.f64(double %a)
ret double %0
@@ -42,18 +44,18 @@ entry:
declare float @llvm.floor.f32(float)
define float @floor_f32(float %a) {
-; MIPS32-LABEL: floor_f32:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $sp, $sp, -24
-; MIPS32-NEXT: .cfi_def_cfa_offset 24
-; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: .cfi_offset 31, -4
-; MIPS32-NEXT: jal floorf
-; MIPS32-NEXT: nop
-; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MIPS32-NEXT: addiu $sp, $sp, 24
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: floor_f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $sp, $sp, -24
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset 31, -4
+; CHECK-NEXT: jal floorf
+; CHECK-NEXT: nop
+; CHECK-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; CHECK-NEXT: addiu $sp, $sp, 24
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%0 = call float @llvm.floor.f32(float %a)
ret float %0
@@ -61,18 +63,18 @@ entry:
declare double @llvm.floor.f64(double)
define double @floor_f64(double %a) {
-; MIPS32-LABEL: floor_f64:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $sp, $sp, -24
-; MIPS32-NEXT: .cfi_def_cfa_offset 24
-; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
-; MIPS32-NEXT: .cfi_offset 31, -4
-; MIPS32-NEXT: jal floor
-; MIPS32-NEXT: nop
-; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
-; MIPS32-NEXT: addiu $sp, $sp, 24
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: floor_f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $sp, $sp, -24
+; CHECK-NEXT: .cfi_def_cfa_offset 24
+; CHECK-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
+; CHECK-NEXT: .cfi_offset 31, -4
+; CHECK-NEXT: jal floor
+; CHECK-NEXT: nop
+; CHECK-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
+; CHECK-NEXT: addiu $sp, $sp, 24
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%0 = call double @llvm.floor.f64(double %a)
ret double %0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll
index e674248a3100..00927689ab5c 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fabs.ll
@@ -1,14 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
declare float @llvm.fabs.f32(float)
define float @fabs_f32(float %a) {
-; MIPS32-LABEL: fabs_f32:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: abs.s $f0, $f12
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: fabs_f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: abs.s $f0, $f12
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%0 = call float @llvm.fabs.f32(float %a)
ret float %0
@@ -16,11 +18,11 @@ entry:
declare double @llvm.fabs.f64(double)
define double @fabs_f64(double %a) {
-; MIPS32-LABEL: fabs_f64:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: abs.d $f0, $f12
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: fabs_f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: abs.d $f0, $f12
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%0 = call double @llvm.fabs.f64(double %a)
ret double %0
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
index bfff4e72d0ab..9d3b7ce079f9 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
@@ -1,23 +1,25 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
define i1 @false_s(float %x, float %y) {
-; MIPS32-LABEL: false_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: ori $2, $zero, 0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: false_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ori $2, $zero, 0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp false float %x, %y
ret i1 %cmp
}
define i1 @true_s(float %x, float %y) {
-; MIPS32-LABEL: true_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: ori $2, $zero, 1
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: true_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ori $2, $zero, 1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp true float %x, %y
ret i1 %cmp
@@ -25,25 +27,25 @@ entry:
define i1 @uno_s(float %x, float %y) {
-; MIPS32-LABEL: uno_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.un.s $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: uno_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.un.s $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp uno float %x, %y
ret i1 %cmp
}
define i1 @ord_s(float %x, float %y) {
-; MIPS32-LABEL: ord_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.un.s $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ord_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.un.s $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ord float %x, %y
ret i1 %cmp
@@ -51,25 +53,25 @@ entry:
define i1 @oeq_s(float %x, float %y) {
-; MIPS32-LABEL: oeq_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.eq.s $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: oeq_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.eq.s $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp oeq float %x, %y
ret i1 %cmp
}
define i1 @une_s(float %x, float %y) {
-; MIPS32-LABEL: une_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.eq.s $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: une_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.eq.s $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp une float %x, %y
ret i1 %cmp
@@ -77,25 +79,25 @@ entry:
define i1 @ueq_s(float %x, float %y) {
-; MIPS32-LABEL: ueq_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ueq.s $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ueq_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ueq.s $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ueq float %x, %y
ret i1 %cmp
}
define i1 @one_s(float %x, float %y) {
-; MIPS32-LABEL: one_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ueq.s $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: one_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ueq.s $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp one float %x, %y
ret i1 %cmp
@@ -103,25 +105,25 @@ entry:
define i1 @olt_s(float %x, float %y) {
-; MIPS32-LABEL: olt_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.olt.s $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: olt_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.olt.s $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp olt float %x, %y
ret i1 %cmp
}
define i1 @uge_s(float %x, float %y) {
-; MIPS32-LABEL: uge_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.olt.s $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: uge_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.olt.s $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp uge float %x, %y
ret i1 %cmp
@@ -129,25 +131,25 @@ entry:
define i1 @ult_s(float %x, float %y) {
-; MIPS32-LABEL: ult_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ult.s $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ult_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ult.s $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ult float %x, %y
ret i1 %cmp
}
define i1 @oge_s(float %x, float %y) {
-; MIPS32-LABEL: oge_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ult.s $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: oge_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ult.s $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp oge float %x, %y
ret i1 %cmp
@@ -155,25 +157,25 @@ entry:
define i1 @ole_s(float %x, float %y) {
-; MIPS32-LABEL: ole_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ole.s $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ole_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ole.s $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ole float %x, %y
ret i1 %cmp
}
define i1 @ugt_s(float %x, float %y) {
-; MIPS32-LABEL: ugt_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ole.s $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ugt_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ole.s $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ugt float %x, %y
ret i1 %cmp
@@ -181,25 +183,25 @@ entry:
define i1 @ule_s(float %x, float %y) {
-; MIPS32-LABEL: ule_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ule.s $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ule_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ule.s $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ule float %x, %y
ret i1 %cmp
}
define i1 @ogt_s(float %x, float %y) {
-; MIPS32-LABEL: ogt_s:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ule.s $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ogt_s:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ule.s $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ogt float %x, %y
ret i1 %cmp
@@ -207,21 +209,21 @@ entry:
define i1 @false_d(double %x, double %y) {
-; MIPS32-LABEL: false_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: ori $2, $zero, 0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: false_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ori $2, $zero, 0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp false double %x, %y
ret i1 %cmp
}
define i1 @true_d(double %x, double %y) {
-; MIPS32-LABEL: true_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: ori $2, $zero, 1
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: true_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: ori $2, $zero, 1
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp true double %x, %y
ret i1 %cmp
@@ -229,25 +231,25 @@ entry:
define i1 @uno_d(double %x, double %y) {
-; MIPS32-LABEL: uno_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.un.d $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: uno_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.un.d $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp uno double %x, %y
ret i1 %cmp
}
define i1 @ord_d(double %x, double %y) {
-; MIPS32-LABEL: ord_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.un.d $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ord_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.un.d $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ord double %x, %y
ret i1 %cmp
@@ -255,25 +257,25 @@ entry:
define i1 @oeq_d(double %x, double %y) {
-; MIPS32-LABEL: oeq_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.eq.d $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: oeq_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.eq.d $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp oeq double %x, %y
ret i1 %cmp
}
define i1 @une_d(double %x, double %y) {
-; MIPS32-LABEL: une_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.eq.d $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: une_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.eq.d $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp une double %x, %y
ret i1 %cmp
@@ -281,25 +283,25 @@ entry:
define i1 @ueq_d(double %x, double %y) {
-; MIPS32-LABEL: ueq_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ueq.d $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ueq_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ueq.d $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ueq double %x, %y
ret i1 %cmp
}
define i1 @one_d(double %x, double %y) {
-; MIPS32-LABEL: one_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ueq.d $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: one_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ueq.d $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp one double %x, %y
ret i1 %cmp
@@ -307,25 +309,25 @@ entry:
define i1 @olt_d(double %x, double %y) {
-; MIPS32-LABEL: olt_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.olt.d $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: olt_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.olt.d $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp olt double %x, %y
ret i1 %cmp
}
define i1 @uge_d(double %x, double %y) {
-; MIPS32-LABEL: uge_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.olt.d $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: uge_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.olt.d $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp uge double %x, %y
ret i1 %cmp
@@ -333,25 +335,25 @@ entry:
define i1 @ult_d(double %x, double %y) {
-; MIPS32-LABEL: ult_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ult.d $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ult_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ult.d $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ult double %x, %y
ret i1 %cmp
}
define i1 @oge_d(double %x, double %y) {
-; MIPS32-LABEL: oge_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ult.d $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: oge_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ult.d $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp oge double %x, %y
ret i1 %cmp
@@ -359,25 +361,25 @@ entry:
define i1 @ole_d(double %x, double %y) {
-; MIPS32-LABEL: ole_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ole.d $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ole_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ole.d $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ole double %x, %y
ret i1 %cmp
}
define i1 @ugt_d(double %x, double %y) {
-; MIPS32-LABEL: ugt_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ole.d $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ugt_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ole.d $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ugt double %x, %y
ret i1 %cmp
@@ -385,25 +387,25 @@ entry:
define i1 @ule_d(double %x, double %y) {
-; MIPS32-LABEL: ule_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ule.d $f12, $f14
-; MIPS32-NEXT: movf $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ule_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ule.d $f12, $f14
+; CHECK-NEXT: movf $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ule double %x, %y
ret i1 %cmp
}
define i1 @ogt_d(double %x, double %y) {
-; MIPS32-LABEL: ogt_d:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: addiu $2, $zero, 1
-; MIPS32-NEXT: c.ule.d $f12, $f14
-; MIPS32-NEXT: movt $2, $zero, $fcc0
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: ogt_d:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addiu $2, $zero, 1
+; CHECK-NEXT: c.ule.d $f12, $f14
+; CHECK-NEXT: movt $2, $zero, $fcc0
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%cmp = fcmp ogt double %x, %y
ret i1 %cmp
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll
index 091640fe6458..3acd365770da 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_arithmetic_operations.ll
@@ -1,90 +1,92 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
define float @float_add(float %a, float %b) {
-; MIPS32-LABEL: float_add:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: add.s $f0, $f12, $f14
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: float_add:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: add.s $f0, $f12, $f14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%add = fadd float %a, %b
ret float %add
}
define float @float_sub(float %a, float %b) {
-; MIPS32-LABEL: float_sub:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: sub.s $f0, $f12, $f14
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: float_sub:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub.s $f0, $f12, $f14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%sub = fsub float %a, %b
ret float %sub
}
define float @float_mul(float %a, float %b) {
-; MIPS32-LABEL: float_mul:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: mul.s $f0, $f12, $f14
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: float_mul:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mul.s $f0, $f12, $f14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%mul = fmul float %a, %b
ret float %mul
}
define float @float_div(float %a, float %b) {
-; MIPS32-LABEL: float_div:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: div.s $f0, $f12, $f14
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: float_div:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: div.s $f0, $f12, $f14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%div = fdiv float %a, %b
ret float %div
}
define double @double_add(double %a, double %b) {
-; MIPS32-LABEL: double_add:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: add.d $f0, $f12, $f14
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: double_add:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: add.d $f0, $f12, $f14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%add = fadd double %a, %b
ret double %add
}
define double @double_sub(double %a, double %b) {
-; MIPS32-LABEL: double_sub:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: sub.d $f0, $f12, $f14
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: double_sub:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sub.d $f0, $f12, $f14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%sub = fsub double %a, %b
ret double %sub
}
define double @double_mul(double %a, double %b) {
-; MIPS32-LABEL: double_mul:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: mul.d $f0, $f12, $f14
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: double_mul:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: mul.d $f0, $f12, $f14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%mul = fmul double %a, %b
ret double %mul
}
define double @double_div(double %a, double %b) {
-; MIPS32-LABEL: double_div:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: div.d $f0, $f12, $f14
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: double_div:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: div.d $f0, $f12, $f14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%div = fdiv double %a, %b
ret double %div
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll
index 2d1965ffa69f..752bcca07b88 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fpext_and_fptrunc.ll
@@ -1,24 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
define double @fpext(float %a) {
-; MIPS32-LABEL: fpext:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: cvt.d.s $f0, $f12
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: fpext:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cvt.d.s $f0, $f12
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%conv = fpext float %a to double
ret double %conv
}
define float @fptrunc(double %a) {
-; MIPS32-LABEL: fptrunc:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: cvt.s.d $f0, $f12
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: fptrunc:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: cvt.s.d $f0, $f12
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%conv = fptrunc double %a to float
ret float %conv
diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll
index 1bca4e893d9c..96913ee6914e 100644
--- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll
+++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fsqrt.ll
@@ -1,14 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
-; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
+; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel \
+; RUN: -verify-machineinstrs %s -o -| FileCheck %s
declare float @llvm.sqrt.f32(float)
define float @sqrt_f32(float %a) {
-; MIPS32-LABEL: sqrt_f32:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: sqrt.s $f0, $f12
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: sqrt_f32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sqrt.s $f0, $f12
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%0 = call float @llvm.sqrt.f32(float %a)
ret float %0
@@ -16,11 +18,11 @@ entry:
declare double @llvm.sqrt.f64(double)
define double @sqrt_f64(double %a) {
-; MIPS32-LABEL: sqrt_f64:
-; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: sqrt.d $f0, $f12
-; MIPS32-NEXT: jr $ra
-; MIPS32-NEXT: nop
+; CHECK-LABEL: sqrt_f64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: sqrt.d $f0, $f12
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: nop
entry:
%0 = call double @llvm.sqrt.f64(double %a)
ret double %0
diff --git a/llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll b/llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll
index ce994c2c18a9..cf8cf7e53931 100644
--- a/llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll
+++ b/llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll
@@ -2,7 +2,7 @@
; RUN: llc -O0 -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r2 -target-abi=o32 < %s -filetype=asm -o - \
; RUN: | FileCheck -check-prefixes=O32 %s
; RUN: llc -O0 -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 -target-abi=n32 < %s -filetype=asm -o - \
-; RUN: | FileCheck -check-prefixes=N32,ALL %s
+; RUN: | FileCheck -check-prefixes=N32 %s
; RUN: llc -O0 -mtriple=mips64el-unknown-linux-gnu -mcpu=mips64r2 -target-abi=n64 < %s -filetype=asm -o - \
; RUN: | FileCheck -check-prefixes=N64 %s
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
index 004f6d94749d..ccb75a4a8b0b 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
@@ -1,5 +1,5 @@
-; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s
-; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s
+; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
+; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
index 14c0391a2529..898d189d202a 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
@@ -1,7 +1,7 @@
; RUN: llc -mtriple=mips-linux -relocation-model=static < %s \
-; RUN: | FileCheck --check-prefixes=ALL,O32,O32-BE %s
+; RUN: | FileCheck --check-prefixes=ALL,O32 %s
; RUN: llc -mtriple=mipsel-linux -relocation-model=static < %s \
-; RUN: | FileCheck --check-prefixes=ALL,O32,O32-LE %s
+; RUN: | FileCheck --check-prefixes=ALL,O32 %s
; RUN-TODO: llc -march=mips64 -relocation-model=static -target-abi o32 < %s \
; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
index bd33e0c51697..1a604e7b5e89 100644
--- a/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
+++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-fpxx.ll
@@ -1,12 +1,12 @@
-; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s
-; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s
-; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s
-; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV %s
+; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
+; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
+; RUN: llc -march=mips -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s
+; RUN: llc -march=mipsel -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV %s
-; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s
-; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX %s
-; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s
-; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=ALL,O32-FPXX-INV,O32-FPXX-INV %s
+; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
+; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX %s
+; RUN-TODO: llc -march=mips64 -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s
+; RUN-TODO: llc -march=mips64el -mattr=+o32,+fpxx < %s | FileCheck --check-prefixes=O32-FPXX-INV,O32-FPXX-INV %s
define void @fpu_clobber() nounwind {
entry:
diff --git a/llvm/test/CodeGen/Mips/cconv/vector.ll b/llvm/test/CodeGen/Mips/cconv/vector.ll
index 071949d7b9e1..99053f3641f0 100644
--- a/llvm/test/CodeGen/Mips/cconv/vector.ll
+++ b/llvm/test/CodeGen/Mips/cconv/vector.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32,MIPS32EB
-; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EB
-; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32R5,MIPS32R5EB
-; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64R5,MIPS64R5EB
-; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32,MIPS32EL
-; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64,MIPS64EL
-; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=ALL,MIPS32R5,MIPS32R5EL
-; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=ALL,MIPS64R5,MIPS64R5EL
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=MIPS32,MIPS32EB
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=MIPS64,MIPS64EB
+; RUN: llc < %s -mtriple=mips-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=MIPS32R5,MIPS32R5EB
+; RUN: llc < %s -mtriple=mips64-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=MIPS64R5,MIPS64R5EB
+; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32 -disable-mips-delay-filler | FileCheck %s --check-prefixes=MIPS32,MIPS32EL
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64 -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=MIPS64,MIPS64EL
+; RUN: llc < %s -mtriple=mipsel-unknown-linux-gnu -mcpu=mips32r5 -mattr=+fp64,+msa -disable-mips-delay-filler | FileCheck %s --check-prefixes=MIPS32R5,MIPS32R5EL
+; RUN: llc < %s -mtriple=mips64el-unknown-linux-gnu -relocation-model=pic -mcpu=mips64r5 -mattr=+fp64,+msa -disable-mips-delay-filler -mips-jalr-reloc=false | FileCheck %s --check-prefixes=MIPS64R5,MIPS64R5EL
; Test that vector types are passed through the integer register set whether or
; not MSA is enabled. This is a ABI requirement for MIPS. For GCC compatibility
diff --git a/llvm/test/CodeGen/Mips/ehframe-indirect.ll b/llvm/test/CodeGen/Mips/ehframe-indirect.ll
index ab799ebed3ce..98a2f389ed04 100644
--- a/llvm/test/CodeGen/Mips/ehframe-indirect.ll
+++ b/llvm/test/CodeGen/Mips/ehframe-indirect.ll
@@ -3,15 +3,17 @@
; RUN: llc -mtriple=mipsel-linux-android < %s -asm-verbose -relocation-model=pic | \
; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-O32,O32 %s
; RUN: llc -mtriple=mips64el-linux-gnu -target-abi=n32 < %s -asm-verbose -relocation-model=pic | \
-; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-N32,N32 %s
+; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-NEW,N32 %s
; RUN: llc -mtriple=mips64el-linux-gnu < %s -asm-verbose -relocation-model=pic | \
-; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-N64,N64 %s
+; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-NEW,N64 %s
; RUN: llc -mtriple=mips64el-linux-android < %s -asm-verbose -relocation-model=pic | \
-; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-N64,N64 %s
+; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-NEW,N64 %s
; RUN: llc -mtriple=mips64el-linux-gnu < %s -asm-verbose -relocation-model=pic | \
-; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-N64,N64 %s
+; RUN: FileCheck -check-prefixes=ALL,LINUX,LINUX-NEW,N64 %s
+; RUN: llc -mtriple=mips-unknown-freebsd11.0 < %s -asm-verbose -relocation-model=pic | \
+; RUN: FileCheck -check-prefixes=ALL,FREEBSD,FREEBSD-O32,O32 %s
; RUN: llc -mtriple=mips64-unknown-freebsd11.0 < %s -asm-verbose -relocation-model=pic | \
-; RUN: FileCheck -check-prefixes=ALL,FREEBSD,FREEBSD-N64,N64 %s
+; RUN: FileCheck -check-prefixes=ALL,FREEBSD,FREEBSD-NEW,N64 %s
@_ZTISt9exception = external constant i8*
diff --git a/llvm/test/CodeGen/Mips/fmadd1.ll b/llvm/test/CodeGen/Mips/fmadd1.ll
index d7f6308ac0b0..4704387bf289 100644
--- a/llvm/test/CodeGen/Mips/fmadd1.ll
+++ b/llvm/test/CodeGen/Mips/fmadd1.ll
@@ -5,29 +5,29 @@
; IEEE 754 (1985) and IEEE 754 (2008). These instructions are therefore only
; available when -enable-no-nans-fp-math is given.
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32-NOMADD
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R2,32R2-NONAN
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NONAN-NOMADD
+; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,32R6-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64,64-NONAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R2,64R2-NONAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
-; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 -enable-no-nans-fp-math | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefixes=ALL,32-NOMADD
; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefixes=ALL,32R2,32R2-NAN
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD,32R6-NAN-NOMADD
+; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefixes=ALL,32R6-NOMADD
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64,64-NAN
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R2,64R2-NAN
-; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64r6 -target-abi=n64 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
; Check that madd.[ds], msub.[ds], nmadd.[ds], and nmsub.[ds] are not generated
; when +nomadd attribute is specified.
; Output for mips32 and mips64r6 reused since aforementioned instructions are
; not generated in those cases.
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NONAN-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NONAN-NOMADD
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD,32-NAN-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD,64R6-NAN-NOMADD
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -enable-no-nans-fp-math -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,32-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
+; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 -mattr=+nomadd4 | FileCheck %s -check-prefixes=ALL,64R6-NOMADD
define float @FOO0float(float %a, float %b, float %c) nounwind readnone {
entry:
diff --git a/llvm/test/CodeGen/Mips/fpbr.ll b/llvm/test/CodeGen/Mips/fpbr.ll
index 7fb508f606b2..251c5392575b 100644
--- a/llvm/test/CodeGen/Mips/fpbr.ll
+++ b/llvm/test/CodeGen/Mips/fpbr.ll
@@ -1,8 +1,8 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,FCC,32-FCC
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,32-FCC
; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,GPR,32-GPR
-; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC
-; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,FCC,64-FCC
+; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefixes=ALL,64-FCC
+; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefixes=ALL,64-FCC
; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefixes=ALL,GPR,64-GPR
define void @func0(float %f2, float %f3) nounwind {
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
index c75bda3f394a..9be26cc88db0 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/mul.ll
@@ -15,11 +15,11 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 -relocation-model=pic | \
-; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
+; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 -relocation-model=pic | \
-; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
+; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 -relocation-model=pic | \
-; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64,GP64-NOT-R6
+; RUN: FileCheck %s -check-prefixes=ALL,64R1-R5,GP64-NOT-R6
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -relocation-model=pic | \
; RUN: FileCheck %s -check-prefixes=ALL,64R6
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -relocation-model=pic | \
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
index 6f9894f9855d..7b3778437066 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/ret.ll
@@ -163,7 +163,7 @@ define float @ret_float_0x0() {
; MTHC1-DAG: mtc1 $zero, $f0
-; DMTC-DAG: dmtc1 $zero, $f0
+; DMTC1-DAG: mtc1 $zero, $f0
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
@@ -195,7 +195,7 @@ define double @ret_double_0x0() {
; MTHC1-DAG: mtc1 $zero, $f0
; MTHC1-DAG: mthc1 $zero, $f0
-; DMTC-DAG: dmtc1 $zero, $f0
+; DMTC1-DAG: dmtc1 $zero, $f0
; NOT-R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JR
; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
index d07051f05e1f..01c046feec87 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
@@ -1,13 +1,13 @@
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
; RUN: -check-prefixes=ALL,M2,M2-M3
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R1
+; RUN: -check-prefixes=ALL,CMOV,CMOV-32
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
+; RUN: -check-prefixes=ALL,CMOV,CMOV-32
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
+; RUN: -check-prefixes=ALL,CMOV,CMOV-32
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
-; RUN: -check-prefixes=ALL,CMOV,CMOV-32,CMOV-32R2-R5
+; RUN: -check-prefixes=ALL,CMOV,CMOV-32
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefixes=ALL,SEL,SEL-32
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
index d839a6e4c88c..51dcccefc84d 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/sub.ll
@@ -1,19 +1,19 @@
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
-; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM,PRE4
+; RUN: -check-prefixes=NOT-R2-R6,GP32,NOT-MM,PRE4
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
-; RUN: -check-prefixes=NOT-R2-R6,GP32,GP32-NOT-MM,NOT-MM
+; RUN: -check-prefixes=NOT-R2-R6,GP32,NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
-; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
+; RUN: -check-prefixes=R2-R6,GP32,NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
-; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
+; RUN: -check-prefixes=R2-R6,GP32,NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
-; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
+; RUN: -check-prefixes=R2-R6,GP32,NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN: -check-prefixes=R2-R6,GP32,GP32-NOT-MM,NOT-MM
+; RUN: -check-prefixes=R2-R6,GP32,NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips -verify-machineinstrs | FileCheck %s \
-; RUN: -check-prefixes=GP32-MM,GP32,MM32,MMR3
+; RUN: -check-prefixes=MM32,MMR3
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
-; RUN: -check-prefixes=GP32-MM,GP32,MM32,MMR6
+; RUN: -check-prefixes=MM32,MMR6
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefixes=NOT-R2-R6,GP64,NOT-MM,GP64-NOT-R2
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
@@ -98,17 +98,17 @@ define signext i64 @sub_i64(i64 signext %a, i64 signext %b) {
entry:
; ALL-LABEL: sub_i64:
- ; GP32-NOT-MM: sltu $[[T0:[0-9]+]], $5, $7
- ; GP32-NOT-MM: subu $2, $4, $6
- ; GP32-NOT-MM: subu $2, $2, $[[T0]]
- ; GP32-NOT-MM: subu $3, $5, $7
+ ; GP32: sltu $[[T0:[0-9]+]], $5, $7
+ ; GP32: subu $2, $4, $6
+ ; GP32: subu $2, $2, $[[T0]]
+ ; GP32: subu $3, $5, $7
- ; MM32: sltu $[[T0:[0-9]+]], $5, $7
- ; MM32: subu16 $3, $4, $6
- ; MM32: subu16 $2, $3, $[[T0]]
- ; MM32: subu16 $3, $5, $7
+ ; MM32: sltu $[[T0:[0-9]+]], $5, $7
+ ; MM32: subu16 $3, $4, $6
+ ; MM32: subu16 $2, $3, $[[T0]]
+ ; MM32: subu16 $3, $5, $7
- ; GP64: dsubu $2, $4, $5
+ ; GP64: dsubu $2, $4, $5
%r = sub i64 %a, %b
ret i64 %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
index 3b7243712024..e3dd347e723b 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/udiv.ll
@@ -1,29 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=mips -mcpu=mips2 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R1
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
; RUN: llc < %s -mtriple=mips -mcpu=mips32 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R0R1
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
; RUN: llc < %s -mtriple=mips -mcpu=mips32r5 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32,GP32R2R5
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP32
; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 -relocation-model=pic \
; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP32R6
; RUN: llc < %s -mtriple=mips64 -mcpu=mips3 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R1
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R0R2
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r3 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r5 -relocation-model=pic \
-; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64,GP64R2R5
+; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefixes=GP64
; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 -relocation-model=pic \
; RUN: -mips-jalr-reloc=false | FileCheck %s -check-prefix=GP64R6
diff --git a/llvm/test/CodeGen/Mips/load-store-left-right.ll b/llvm/test/CodeGen/Mips/load-store-left-right.ll
index b998772d367c..69ad307df7af 100644
--- a/llvm/test/CodeGen/Mips/load-store-left-right.ll
+++ b/llvm/test/CodeGen/Mips/load-store-left-right.ll
@@ -10,8 +10,8 @@
; RUN: llc -march=mips64 -mcpu=mips64 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64-EB %s
; RUN: llc -march=mips64el -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64R2-EL %s
; RUN: llc -march=mips64 -mcpu=mips64r2 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64,MIPS64R2-EB %s
-; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EL %s
-; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6,MIPS64R6-EB %s
+; RUN: llc -march=mips64el -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6 %s
+; RUN: llc -march=mips64 -mcpu=mips64r6 -target-abi=n64 -relocation-model=pic < %s | FileCheck -check-prefixes=ALL,MIPS64R6 %s
%struct.SLL = type { i64 }
%struct.SI = type { i32 }
diff --git a/llvm/test/CodeGen/Mips/madd-msub.ll b/llvm/test/CodeGen/Mips/madd-msub.ll
index b413dca43863..8d261c1880e3 100644
--- a/llvm/test/CodeGen/Mips/madd-msub.ll
+++ b/llvm/test/CodeGen/Mips/madd-msub.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=ALL,32
-; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=ALL,32
-; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=ALL,32R6
+; RUN: llc -march=mips -mcpu=mips32 < %s | FileCheck %s -check-prefixes=32
+; RUN: llc -march=mips -mcpu=mips32r2 < %s | FileCheck %s -check-prefixes=32
+; RUN: llc -march=mips -mcpu=mips32r6 < %s | FileCheck %s -check-prefixes=32R6
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=DSP
-; RUN: llc -march=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64
-; RUN: llc -march=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64
-; RUN: llc -march=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=ALL,64R6
-; RUN: llc -march=mips -mattr=mips16 < %s | FileCheck %s -check-prefixes=ALL,16
+; RUN: llc -march=mips -mcpu=mips64 -target-abi n64 < %s | FileCheck %s -check-prefixes=64
+; RUN: llc -march=mips -mcpu=mips64r2 -target-abi n64 < %s | FileCheck %s -check-prefixes=64
+; RUN: llc -march=mips -mcpu=mips64r6 -target-abi n64 < %s | FileCheck %s -check-prefixes=64R6
+; RUN: llc -march=mips -mattr=mips16 < %s | FileCheck %s -check-prefixes=16
define i64 @madd1(i32 %a, i32 %b, i32 %c) nounwind readnone {
; 32-LABEL: madd1:
diff --git a/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll b/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
index b08ea6bfbff1..787719338a39 100644
--- a/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
+++ b/llvm/test/CodeGen/Mips/micromips-lwc1-swc1.ll
@@ -1,9 +1,9 @@
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips \
; RUN: -relocation-model=pic < %s | \
-; RUN: FileCheck %s -check-prefixes=ALL,MM32
+; RUN: FileCheck %s -check-prefixes=MM32
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips \
; RUN: -relocation-model=pic < %s | \
-; RUN: FileCheck %s -check-prefixes=ALL,MM32
+; RUN: FileCheck %s -check-prefixes=MM32
@gf0 = external global float
diff --git a/llvm/test/CodeGen/Mips/mips64shift.ll b/llvm/test/CodeGen/Mips/mips64shift.ll
index 0b1294d3afb8..ca09d2f5b290 100644
--- a/llvm/test/CodeGen/Mips/mips64shift.ll
+++ b/llvm/test/CodeGen/Mips/mips64shift.ll
@@ -1,64 +1,64 @@
-; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck -check-prefixes=ALL,MIPS %s
+; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; ALL: dsllv
+; CHECK: dsllv
%shl = shl i64 %a0, %a1
ret i64 %shl
}
define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; ALL: dsrav
+; CHECK: dsrav
%shr = ashr i64 %a0, %a1
ret i64 %shr
}
define i64 @f2(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; ALL: dsrlv
+; CHECK: dsrlv
%shr = lshr i64 %a0, %a1
ret i64 %shr
}
define i64 @f3(i64 %a0) nounwind readnone {
entry:
-; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
+; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
%shl = shl i64 %a0, 10
ret i64 %shl
}
define i64 @f4(i64 %a0) nounwind readnone {
entry:
-; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
+; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
%shr = ashr i64 %a0, 10
ret i64 %shr
}
define i64 @f5(i64 %a0) nounwind readnone {
entry:
-; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
+; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
%shr = lshr i64 %a0, 10
ret i64 %shr
}
define i64 @f6(i64 %a0) nounwind readnone {
entry:
-; ALL: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
+; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
%shl = shl i64 %a0, 40
ret i64 %shl
}
define i64 @f7(i64 %a0) nounwind readnone {
entry:
-; ALL: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
+; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
%shr = ashr i64 %a0, 40
ret i64 %shr
}
define i64 @f8(i64 %a0) nounwind readnone {
entry:
-; ALL: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
+; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
%shr = lshr i64 %a0, 40
ret i64 %shr
}
@@ -66,7 +66,7 @@ entry:
define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
entry:
; CHECK-NOT: sll
-; ALL: drotrv
+; CHECK: drotrv
%shr = lshr i64 %a0, %a1
%sub = sub i64 64, %a1
%shl = shl i64 %a0, %sub
@@ -76,8 +76,7 @@ entry:
define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
entry:
-; CHECK-NOT: sll
-; ALL: drotrv
+; CHECK: drotrv
%shl = shl i64 %a0, %a1
%sub = sub i64 64, %a1
%shr = lshr i64 %a0, %sub
@@ -87,7 +86,7 @@ entry:
define i64 @f11(i64 %a0) nounwind readnone {
entry:
-; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
+; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
%shr = lshr i64 %a0, 10
%shl = shl i64 %a0, 54
%or = or i64 %shr, %shl
@@ -96,11 +95,9 @@ entry:
define i64 @f12(i64 %a0) nounwind readnone {
entry:
-; ALL: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
+; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
%shl = shl i64 %a0, 10
%shr = lshr i64 %a0, 54
%or = or i64 %shl, %shr
ret i64 %or
}
-
-
diff --git a/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll b/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
index 0260afaa1860..50880fb8303c 100644
--- a/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
+++ b/llvm/test/CodeGen/Mips/mno-ldc1-sdc1.ll
@@ -55,7 +55,7 @@
; RUN: -mcpu=mips32r6 < %s | \
; RUN: FileCheck %s -check-prefixes=ALL,32R6,32R6-LE,32R6-LE-STATIC
; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r3 \
-; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC_PIC
+; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC-PIC
; RUN: llc -march=mipsel -relocation-model=static -mcpu=mips32r6 \
; RUN: -mattr=+micromips < %s | FileCheck %s -check-prefixes=ALL,MM-STATIC-PIC
diff --git a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
index 3c1aa8b4792b..f1f1ba692966 100644
--- a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
+++ b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
@@ -1,23 +1,23 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -mtriple=mipsel-- -mcpu=mips32r5 -mattr=+abs2008 \
; RUN: -mattr=+fp64,+msa -verify-machineinstrs -mips-jalr-reloc=false < %s | FileCheck %s \
-; RUN: --check-prefixes=ALL,MIPS32,MIPSR5,MIPS32-O32,MIPS32R5-O32
+; RUN: --check-prefixes=MIPS32,MIPS32-O32
; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r5 -mattr=+abs2008 \
; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n32 -mips-jalr-reloc=false < %s | FileCheck %s \
-; RUN: --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N32,MIPS64R5-N32
+; RUN: --check-prefixes=MIPS64-N32,MIPS64R5-N32
; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r5 -mattr=+abs2008 \
; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n64 -mips-jalr-reloc=false < %s | FileCheck %s \
-; RUN: --check-prefixes=ALL,MIPS64,MIPSR5,MIPS64-N64,MIPS64R5-N64
+; RUN: --check-prefixes=MIPS64-N64,MIPS64R5-N64
; RUN: llc -relocation-model=pic -mtriple=mipsel-- -mcpu=mips32r6 \
; RUN: -mattr=+fp64,+msa -verify-machineinstrs -mips-jalr-reloc=false < %s | FileCheck %s \
-; RUN: --check-prefixes=ALL,MIPS32,MIPSR6,MIPSR6-O32
+; RUN: --check-prefixes=MIPS32,MIPSR6-O32
; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r6 \
; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n32 -mips-jalr-reloc=false < %s | FileCheck %s \
-; RUN: --check-prefixes=ALL,MIPS64,MIPSR6,MIPS64-N32,MIPSR6-N32
+; RUN: --check-prefixes=MIPS64-N32,MIPSR6-N32
; RUN: llc -relocation-model=pic -mtriple=mips64el-- -mcpu=mips64r6 \
; RUN: -mattr=+fp64,+msa -verify-machineinstrs -target-abi n64 -mips-jalr-reloc=false < %s | FileCheck %s \
-; RUN: --check-prefixes=ALL,MIPS64,MIPSR6,MIPS64-N64,MIPSR6-N64
+; RUN: --check-prefixes=MIPS64-N64,MIPSR6-N64
; Check the use of frame indexes in the msa pseudo f16 instructions.
diff --git a/llvm/test/CodeGen/Mips/msa/frameindex.ll b/llvm/test/CodeGen/Mips/msa/frameindex.ll
index f71caf4e87ea..94c3fd85a565 100644
--- a/llvm/test/CodeGen/Mips/msa/frameindex.ll
+++ b/llvm/test/CodeGen/Mips/msa/frameindex.ll
@@ -1,110 +1,108 @@
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s \
-; RUN: | FileCheck -check-prefixes=MIPS32-AE,MIPS32-BE %s
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \
-; RUN: | FileCheck -check-prefixes=MIPS32-AE,MIPS32-LE %s
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
define void @loadstore_v16i8_near() nounwind {
- ; MIPS32-AE: loadstore_v16i8_near:
+ ; CHECK: loadstore_v16i8_near:
%1 = alloca <16 x i8>
%2 = load volatile <16 x i8>, <16 x i8>* %1
- ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0($sp)
+ ; CHECK: ld.b [[R1:\$w[0-9]+]], 0($sp)
store volatile <16 x i8> %2, <16 x i8>* %1
- ; MIPS32-AE: st.b [[R1]], 0($sp)
+ ; CHECK: st.b [[R1]], 0($sp)
ret void
- ; MIPS32-AE: .size loadstore_v16i8_near
+ ; CHECK: .size loadstore_v16i8_near
}
define void @loadstore_v16i8_just_under_simm10() nounwind {
- ; MIPS32-AE: loadstore_v16i8_just_under_simm10:
+ ; CHECK: loadstore_v16i8_just_under_simm10:
%1 = alloca <16 x i8>
%2 = alloca [492 x i8] ; Push the frame--acounting for the emergency spill
; slot--right up to 512 bytes
%3 = load volatile <16 x i8>, <16 x i8>* %1
- ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 496($sp)
+ ; CHECK: ld.b [[R1:\$w[0-9]+]], 496($sp)
store volatile <16 x i8> %3, <16 x i8>* %1
- ; MIPS32-AE: st.b [[R1]], 496($sp)
+ ; CHECK: st.b [[R1]], 496($sp)
ret void
- ; MIPS32-AE: .size loadstore_v16i8_just_under_simm10
+ ; CHECK: .size loadstore_v16i8_just_under_simm10
}
define void @loadstore_v16i8_just_over_simm10() nounwind {
- ; MIPS32-AE: loadstore_v16i8_just_over_simm10:
+ ; CHECK: loadstore_v16i8_just_over_simm10:
%1 = alloca <16 x i8>
%2 = alloca [497 x i8] ; Push the frame--acounting for the emergency spill
; slot--right up to 512 bytes
%3 = load volatile <16 x i8>, <16 x i8>* %1
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
- ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
+ ; CHECK: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <16 x i8> %3, <16 x i8>* %1
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
- ; MIPS32-AE: st.b [[R1]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 512
+ ; CHECK: st.b [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v16i8_just_over_simm10
+ ; CHECK: .size loadstore_v16i8_just_over_simm10
}
define void @loadstore_v16i8_just_under_simm16() nounwind {
- ; MIPS32-AE: loadstore_v16i8_just_under_simm16:
+ ; CHECK: loadstore_v16i8_just_under_simm16:
%1 = alloca <16 x i8>
%2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
; slot--right up to 32768 bytes
%3 = load volatile <16 x i8>, <16 x i8>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <16 x i8> %3, <16 x i8>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: st.b [[R1]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: st.b [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v16i8_just_under_simm16
+ ; CHECK: .size loadstore_v16i8_just_under_simm16
}
define void @loadstore_v16i8_just_over_simm16() nounwind {
- ; MIPS32-AE: loadstore_v16i8_just_over_simm16:
+ ; CHECK: loadstore_v16i8_just_over_simm16:
%1 = alloca <16 x i8>
%2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
; slot--just over 32768 bytes
%3 = load volatile <16 x i8>, <16 x i8>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: ld.b [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <16 x i8> %3, <16 x i8>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: st.b [[R1]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: st.b [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v16i8_just_over_simm16
+ ; CHECK: .size loadstore_v16i8_just_over_simm16
}
define void @loadstore_v8i16_near() nounwind {
- ; MIPS32-AE: loadstore_v8i16_near:
+ ; CHECK: loadstore_v8i16_near:
%1 = alloca <8 x i16>
%2 = load volatile <8 x i16>, <8 x i16>* %1
- ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0($sp)
+ ; CHECK: ld.h [[R1:\$w[0-9]+]], 0($sp)
store volatile <8 x i16> %2, <8 x i16>* %1
- ; MIPS32-AE: st.h [[R1]], 0($sp)
+ ; CHECK: st.h [[R1]], 0($sp)
ret void
- ; MIPS32-AE: .size loadstore_v8i16_near
+ ; CHECK: .size loadstore_v8i16_near
}
define void @loadstore_v8i16_unaligned() nounwind {
- ; MIPS32-AE: loadstore_v8i16_unaligned:
+ ; CHECK: loadstore_v8i16_unaligned:
%1 = alloca [2 x <8 x i16>]
%2 = bitcast [2 x <8 x i16>]* %1 to i8*
@@ -113,105 +111,105 @@ define void @loadstore_v8i16_unaligned() nounwind {
%5 = getelementptr [2 x <8 x i16>], [2 x <8 x i16>]* %4, i32 0, i32 0
%6 = load volatile <8 x i16>, <8 x i16>* %5
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
- ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
+ ; CHECK: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %6, <8 x i16>* %5
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
- ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
+ ; CHECK: st.h [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v8i16_unaligned
+ ; CHECK: .size loadstore_v8i16_unaligned
}
define void @loadstore_v8i16_just_under_simm10() nounwind {
- ; MIPS32-AE: loadstore_v8i16_just_under_simm10:
+ ; CHECK: loadstore_v8i16_just_under_simm10:
%1 = alloca <8 x i16>
%2 = alloca [1004 x i8] ; Push the frame--acounting for the emergency spill
; slot--right up to 1024 bytes
%3 = load volatile <8 x i16>, <8 x i16>* %1
- ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 1008($sp)
+ ; CHECK: ld.h [[R1:\$w[0-9]+]], 1008($sp)
store volatile <8 x i16> %3, <8 x i16>* %1
- ; MIPS32-AE: st.h [[R1]], 1008($sp)
+ ; CHECK: st.h [[R1]], 1008($sp)
ret void
- ; MIPS32-AE: .size loadstore_v8i16_just_under_simm10
+ ; CHECK: .size loadstore_v8i16_just_under_simm10
}
define void @loadstore_v8i16_just_over_simm10() nounwind {
- ; MIPS32-AE: loadstore_v8i16_just_over_simm10:
+ ; CHECK: loadstore_v8i16_just_over_simm10:
%1 = alloca <8 x i16>
%2 = alloca [1009 x i8] ; Push the frame--acounting for the emergency spill
; slot--just over 1024 bytes
%3 = load volatile <8 x i16>, <8 x i16>* %1
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
- ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
+ ; CHECK: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %3, <8 x i16>* %1
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
- ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1024
+ ; CHECK: st.h [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v8i16_just_over_simm10
+ ; CHECK: .size loadstore_v8i16_just_over_simm10
}
define void @loadstore_v8i16_just_under_simm16() nounwind {
- ; MIPS32-AE: loadstore_v8i16_just_under_simm16:
+ ; CHECK: loadstore_v8i16_just_under_simm16:
%1 = alloca <8 x i16>
%2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
; slot--right up to 32768 bytes
%3 = load volatile <8 x i16>, <8 x i16>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %3, <8 x i16>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: st.h [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v8i16_just_under_simm16
+ ; CHECK: .size loadstore_v8i16_just_under_simm16
}
define void @loadstore_v8i16_just_over_simm16() nounwind {
- ; MIPS32-AE: loadstore_v8i16_just_over_simm16:
+ ; CHECK: loadstore_v8i16_just_over_simm16:
%1 = alloca <8 x i16>
%2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
; slot--just over 32768 bytes
%3 = load volatile <8 x i16>, <8 x i16>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: ld.h [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <8 x i16> %3, <8 x i16>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: st.h [[R1]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: st.h [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v8i16_just_over_simm16
+ ; CHECK: .size loadstore_v8i16_just_over_simm16
}
define void @loadstore_v4i32_near() nounwind {
- ; MIPS32-AE: loadstore_v4i32_near:
+ ; CHECK: loadstore_v4i32_near:
%1 = alloca <4 x i32>
%2 = load volatile <4 x i32>, <4 x i32>* %1
- ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0($sp)
+ ; CHECK: ld.w [[R1:\$w[0-9]+]], 0($sp)
store volatile <4 x i32> %2, <4 x i32>* %1
- ; MIPS32-AE: st.w [[R1]], 0($sp)
+ ; CHECK: st.w [[R1]], 0($sp)
ret void
- ; MIPS32-AE: .size loadstore_v4i32_near
+ ; CHECK: .size loadstore_v4i32_near
}
define void @loadstore_v4i32_unaligned() nounwind {
- ; MIPS32-AE: loadstore_v4i32_unaligned:
+ ; CHECK: loadstore_v4i32_unaligned:
%1 = alloca [2 x <4 x i32>]
%2 = bitcast [2 x <4 x i32>]* %1 to i8*
@@ -220,105 +218,105 @@ define void @loadstore_v4i32_unaligned() nounwind {
%5 = getelementptr [2 x <4 x i32>], [2 x <4 x i32>]* %4, i32 0, i32 0
%6 = load volatile <4 x i32>, <4 x i32>* %5
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
- ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
+ ; CHECK: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %6, <4 x i32>* %5
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
- ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
+ ; CHECK: st.w [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v4i32_unaligned
+ ; CHECK: .size loadstore_v4i32_unaligned
}
define void @loadstore_v4i32_just_under_simm10() nounwind {
- ; MIPS32-AE: loadstore_v4i32_just_under_simm10:
+ ; CHECK: loadstore_v4i32_just_under_simm10:
%1 = alloca <4 x i32>
%2 = alloca [2028 x i8] ; Push the frame--acounting for the emergency spill
; slot--right up to 2048 bytes
%3 = load volatile <4 x i32>, <4 x i32>* %1
- ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 2032($sp)
+ ; CHECK: ld.w [[R1:\$w[0-9]+]], 2032($sp)
store volatile <4 x i32> %3, <4 x i32>* %1
- ; MIPS32-AE: st.w [[R1]], 2032($sp)
+ ; CHECK: st.w [[R1]], 2032($sp)
ret void
- ; MIPS32-AE: .size loadstore_v4i32_just_under_simm10
+ ; CHECK: .size loadstore_v4i32_just_under_simm10
}
define void @loadstore_v4i32_just_over_simm10() nounwind {
- ; MIPS32-AE: loadstore_v4i32_just_over_simm10:
+ ; CHECK: loadstore_v4i32_just_over_simm10:
%1 = alloca <4 x i32>
%2 = alloca [2033 x i8] ; Push the frame--acounting for the emergency spill
; slot--just over 2048 bytes
%3 = load volatile <4 x i32>, <4 x i32>* %1
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
- ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
+ ; CHECK: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %3, <4 x i32>* %1
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
- ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 2048
+ ; CHECK: st.w [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v4i32_just_over_simm10
+ ; CHECK: .size loadstore_v4i32_just_over_simm10
}
define void @loadstore_v4i32_just_under_simm16() nounwind {
- ; MIPS32-AE: loadstore_v4i32_just_under_simm16:
+ ; CHECK: loadstore_v4i32_just_under_simm16:
%1 = alloca <4 x i32>
%2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
; slot-- right up to 32768 bytes
%3 = load volatile <4 x i32>, <4 x i32>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %3, <4 x i32>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: st.w [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v4i32_just_under_simm16
+ ; CHECK: .size loadstore_v4i32_just_under_simm16
}
define void @loadstore_v4i32_just_over_simm16() nounwind {
- ; MIPS32-AE: loadstore_v4i32_just_over_simm16:
+ ; CHECK: loadstore_v4i32_just_over_simm16:
%1 = alloca <4 x i32>
%2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
; slot--just over 32768 bytes
%3 = load volatile <4 x i32>, <4 x i32>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: ld.w [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <4 x i32> %3, <4 x i32>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: st.w [[R1]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: st.w [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v4i32_just_over_simm16
+ ; CHECK: .size loadstore_v4i32_just_over_simm16
}
define void @loadstore_v2i64_near() nounwind {
- ; MIPS32-AE: loadstore_v2i64_near:
+ ; CHECK: loadstore_v2i64_near:
%1 = alloca <2 x i64>
%2 = load volatile <2 x i64>, <2 x i64>* %1
- ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0($sp)
+ ; CHECK: ld.d [[R1:\$w[0-9]+]], 0($sp)
store volatile <2 x i64> %2, <2 x i64>* %1
- ; MIPS32-AE: st.d [[R1]], 0($sp)
+ ; CHECK: st.d [[R1]], 0($sp)
ret void
- ; MIPS32-AE: .size loadstore_v2i64_near
+ ; CHECK: .size loadstore_v2i64_near
}
define void @loadstore_v2i64_unaligned() nounwind {
- ; MIPS32-AE: loadstore_v2i64_unaligned:
+ ; CHECK: loadstore_v2i64_unaligned:
%1 = alloca [2 x <2 x i64>]
%2 = bitcast [2 x <2 x i64>]* %1 to i8*
@@ -327,85 +325,85 @@ define void @loadstore_v2i64_unaligned() nounwind {
%5 = getelementptr [2 x <2 x i64>], [2 x <2 x i64>]* %4, i32 0, i32 0
%6 = load volatile <2 x i64>, <2 x i64>* %5
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
- ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
+ ; CHECK: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %6, <2 x i64>* %5
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
- ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 1
+ ; CHECK: st.d [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v2i64_unaligned
+ ; CHECK: .size loadstore_v2i64_unaligned
}
define void @loadstore_v2i64_just_under_simm10() nounwind {
- ; MIPS32-AE: loadstore_v2i64_just_under_simm10:
+ ; CHECK: loadstore_v2i64_just_under_simm10:
%1 = alloca <2 x i64>
%2 = alloca [4076 x i8] ; Push the frame--acounting for the emergency spill
; slot--right up to 4096 bytes
%3 = load volatile <2 x i64>, <2 x i64>* %1
- ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 4080($sp)
+ ; CHECK: ld.d [[R1:\$w[0-9]+]], 4080($sp)
store volatile <2 x i64> %3, <2 x i64>* %1
- ; MIPS32-AE: st.d [[R1]], 4080($sp)
+ ; CHECK: st.d [[R1]], 4080($sp)
ret void
- ; MIPS32-AE: .size loadstore_v2i64_just_under_simm10
+ ; CHECK: .size loadstore_v2i64_just_under_simm10
}
define void @loadstore_v2i64_just_over_simm10() nounwind {
- ; MIPS32-AE: loadstore_v2i64_just_over_simm10:
+ ; CHECK: loadstore_v2i64_just_over_simm10:
%1 = alloca <2 x i64>
%2 = alloca [4081 x i8] ; Push the frame--acounting for the emergency spill
; slot--just over 4096 bytes
%3 = load volatile <2 x i64>, <2 x i64>* %1
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
- ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
+ ; CHECK: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %3, <2 x i64>* %1
- ; MIPS32-AE: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
- ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
+ ; CHECK: addiu [[BASE:\$([0-9]+|gp)]], $sp, 4096
+ ; CHECK: st.d [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v2i64_just_over_simm10
+ ; CHECK: .size loadstore_v2i64_just_over_simm10
}
define void @loadstore_v2i64_just_under_simm16() nounwind {
- ; MIPS32-AE: loadstore_v2i64_just_under_simm16:
+ ; CHECK: loadstore_v2i64_just_under_simm16:
%1 = alloca <2 x i64>
%2 = alloca [32752 x i8] ; Push the frame--acounting for the emergency spill
; slot--right up to 32768 bytes
%3 = load volatile <2 x i64>, <2 x i64>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %3, <2 x i64>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: st.d [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v2i64_just_under_simm16
+ ; CHECK: .size loadstore_v2i64_just_under_simm16
}
define void @loadstore_v2i64_just_over_simm16() nounwind {
- ; MIPS32-AE: loadstore_v2i64_just_over_simm16:
+ ; CHECK: loadstore_v2i64_just_over_simm16:
%1 = alloca <2 x i64>
%2 = alloca [32753 x i8] ; Push the frame--acounting for the emergency spill
; slot--just over 32768 bytes
%3 = load volatile <2 x i64>, <2 x i64>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: ld.d [[R1:\$w[0-9]+]], 0([[BASE]])
store volatile <2 x i64> %3, <2 x i64>* %1
- ; MIPS32-AE: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
- ; MIPS32-AE: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
- ; MIPS32-AE: st.d [[R1]], 0([[BASE]])
+ ; CHECK: ori [[R2:\$([0-9]+|gp)]], $zero, 32768
+ ; CHECK: addu [[BASE:\$([0-9]+|gp)]], $sp, [[R2]]
+ ; CHECK: st.d [[R1]], 0([[BASE]])
ret void
- ; MIPS32-AE: .size loadstore_v2i64_just_over_simm16
+ ; CHECK: .size loadstore_v2i64_just_over_simm16
}
diff --git a/llvm/test/CodeGen/Mips/msa/i5-s.ll b/llvm/test/CodeGen/Mips/msa/i5-s.ll
index cbc21edfa52f..179320e0813c 100644
--- a/llvm/test/CodeGen/Mips/msa/i5-s.ll
+++ b/llvm/test/CodeGen/Mips/msa/i5-s.ll
@@ -1,8 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r2 < %s \
-; RUN: | FileCheck %s --check-prefixes=ALL,MIPS
-; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r2 < %s \
-; RUN: | FileCheck %s --check-prefixes=ALL,MIPSEL
+; RUN: llc -march=mips -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
+; RUN: llc -march=mipsel -mattr=+msa,+fp64,+mips32r5 < %s | FileCheck %s
; Test the MSA intrinsics that are encoded with the I5 instruction format.
; There are lots of these so this covers those beginning with 's'
@@ -11,16 +9,16 @@
@llvm_mips_subvi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_subvi_b_test() nounwind {
-; ALL-LABEL: llvm_mips_subvi_b_test:
-; ALL: # %bb.0: # %entry
-; ALL-NEXT: lui $1, %hi(llvm_mips_subvi_b_RES)
-; ALL-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_b_RES)
-; ALL-NEXT: lui $2, %hi(llvm_mips_subvi_b_ARG1)
-; ALL-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_b_ARG1)
-; ALL-NEXT: ld.b $w0, 0($2)
-; ALL-NEXT: subvi.b $w0, $w0, 14
-; ALL-NEXT: jr $ra
-; ALL-NEXT: st.b $w0, 0($1)
+; CHECK-LABEL: llvm_mips_subvi_b_test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_b_RES)
+; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_b_RES)
+; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_b_ARG1)
+; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_b_ARG1)
+; CHECK-NEXT: ld.b $w0, 0($2)
+; CHECK-NEXT: subvi.b $w0, $w0, 14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: st.b $w0, 0($1)
entry:
%0 = load <16 x i8>, <16 x i8>* @llvm_mips_subvi_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.subvi.b(<16 x i8> %0, i32 14)
@@ -34,16 +32,16 @@ declare <16 x i8> @llvm.mips.subvi.b(<16 x i8>, i32) nounwind
@llvm_mips_subvi_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
define void @llvm_mips_subvi_h_test() nounwind {
-; ALL-LABEL: llvm_mips_subvi_h_test:
-; ALL: # %bb.0: # %entry
-; ALL-NEXT: lui $1, %hi(llvm_mips_subvi_h_RES)
-; ALL-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_h_RES)
-; ALL-NEXT: lui $2, %hi(llvm_mips_subvi_h_ARG1)
-; ALL-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_h_ARG1)
-; ALL-NEXT: ld.h $w0, 0($2)
-; ALL-NEXT: subvi.h $w0, $w0, 14
-; ALL-NEXT: jr $ra
-; ALL-NEXT: st.h $w0, 0($1)
+; CHECK-LABEL: llvm_mips_subvi_h_test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_h_RES)
+; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_h_RES)
+; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_h_ARG1)
+; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_h_ARG1)
+; CHECK-NEXT: ld.h $w0, 0($2)
+; CHECK-NEXT: subvi.h $w0, $w0, 14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: st.h $w0, 0($1)
entry:
%0 = load <8 x i16>, <8 x i16>* @llvm_mips_subvi_h_ARG1
%1 = tail call <8 x i16> @llvm.mips.subvi.h(<8 x i16> %0, i32 14)
@@ -57,16 +55,16 @@ declare <8 x i16> @llvm.mips.subvi.h(<8 x i16>, i32) nounwind
@llvm_mips_subvi_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
define void @llvm_mips_subvi_w_test() nounwind {
-; ALL-LABEL: llvm_mips_subvi_w_test:
-; ALL: # %bb.0: # %entry
-; ALL-NEXT: lui $1, %hi(llvm_mips_subvi_w_RES)
-; ALL-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_w_RES)
-; ALL-NEXT: lui $2, %hi(llvm_mips_subvi_w_ARG1)
-; ALL-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_w_ARG1)
-; ALL-NEXT: ld.w $w0, 0($2)
-; ALL-NEXT: subvi.w $w0, $w0, 14
-; ALL-NEXT: jr $ra
-; ALL-NEXT: st.w $w0, 0($1)
+; CHECK-LABEL: llvm_mips_subvi_w_test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_w_RES)
+; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_w_RES)
+; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_w_ARG1)
+; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_w_ARG1)
+; CHECK-NEXT: ld.w $w0, 0($2)
+; CHECK-NEXT: subvi.w $w0, $w0, 14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: st.w $w0, 0($1)
entry:
%0 = load <4 x i32>, <4 x i32>* @llvm_mips_subvi_w_ARG1
%1 = tail call <4 x i32> @llvm.mips.subvi.w(<4 x i32> %0, i32 14)
@@ -80,16 +78,16 @@ declare <4 x i32> @llvm.mips.subvi.w(<4 x i32>, i32) nounwind
@llvm_mips_subvi_d_RES = global <2 x i64> <i64 0, i64 0>, align 16
define void @llvm_mips_subvi_d_test() nounwind {
-; ALL-LABEL: llvm_mips_subvi_d_test:
-; ALL: # %bb.0: # %entry
-; ALL-NEXT: lui $1, %hi(llvm_mips_subvi_d_RES)
-; ALL-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_d_RES)
-; ALL-NEXT: lui $2, %hi(llvm_mips_subvi_d_ARG1)
-; ALL-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_d_ARG1)
-; ALL-NEXT: ld.d $w0, 0($2)
-; ALL-NEXT: subvi.d $w0, $w0, 14
-; ALL-NEXT: jr $ra
-; ALL-NEXT: st.d $w0, 0($1)
+; CHECK-LABEL: llvm_mips_subvi_d_test:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui $1, %hi(llvm_mips_subvi_d_RES)
+; CHECK-NEXT: addiu $1, $1, %lo(llvm_mips_subvi_d_RES)
+; CHECK-NEXT: lui $2, %hi(llvm_mips_subvi_d_ARG1)
+; CHECK-NEXT: addiu $2, $2, %lo(llvm_mips_subvi_d_ARG1)
+; CHECK-NEXT: ld.d $w0, 0($2)
+; CHECK-NEXT: subvi.d $w0, $w0, 14
+; CHECK-NEXT: jr $ra
+; CHECK-NEXT: st.d $w0, 0($1)
entry:
%0 = load <2 x i64>, <2 x i64>* @llvm_mips_subvi_d_ARG1
%1 = tail call <2 x i64> @llvm.mips.subvi.d(<2 x i64> %0, i32 14)
diff --git a/llvm/test/CodeGen/Mips/reloc-jalr.ll b/llvm/test/CodeGen/Mips/reloc-jalr.ll
index ef360266a1bb..10fc3ac5f5af 100644
--- a/llvm/test/CodeGen/Mips/reloc-jalr.ll
+++ b/llvm/test/CodeGen/Mips/reloc-jalr.ll
@@ -105,6 +105,7 @@ entry:
; JALR-32: .reloc ([[TMPLABEL:\$.+]]), R_MIPS_JALR, foo
; JALR-64: .reloc [[TMPLABEL:\..+]], R_MIPS_JALR, foo
; JALR-MM: .reloc ([[TMPLABEL:\$.+]]), R_MICROMIPS_JALR, foo
+; NORELOC-NOT: .reloc
; JALR-ALL-NEXT: [[TMPLABEL]]:
; JALR-32R2-NEXT: jalr $25
; JALR-64R2-NEXT: jalr $25
@@ -124,6 +125,7 @@ entry:
; JALR-64: .reloc [[TMPLABEL:\..+]], R_MIPS_JALR, foo
; JALR-MM: .reloc ([[TMPLABEL:\$.+]]), R_MICROMIPS_JALR, foo
; JALR-ALL-NEXT: [[TMPLABEL]]:
+; NORELOC-NOT: .reloc
; TAILCALL-32R2-NEXT: jr $25
; TAILCALL-64R2-NEXT: jr $25
; TAILCALL-MM-NEXT: jrc $25
@@ -178,6 +180,7 @@ entry:
; JALR-ALL: .reloc {{.+}}MIPS_JALR, __tls_get_addr
; ALL-NOT: MIPS_JALR
; JALR-ALL: .reloc {{.+}}MIPS_JALR, __tls_get_addr
+; NORELOC-NOT: .reloc
; ALL-NOT: _MIPS_JALR
%func_gd = load void()*, void()** @tls_fnptr_gd
call void %func_gd()
diff --git a/llvm/test/CodeGen/Mips/unalignedload.ll b/llvm/test/CodeGen/Mips/unalignedload.ll
index ba476b6c4554..9a4a0456a7e5 100644
--- a/llvm/test/CodeGen/Mips/unalignedload.ll
+++ b/llvm/test/CodeGen/Mips/unalignedload.ll
@@ -1,9 +1,9 @@
-; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL
-; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB
-; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32-EL
-; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32-EB
-; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EL,MIPS32R6-EL
-; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,ALL-EB,MIPS32R6-EB
+; RUN: llc < %s -march=mipsel -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32-EL
+; RUN: llc < %s -march=mips -mcpu=mips32 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32-EB
+; RUN: llc < %s -march=mipsel -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32-EL
+; RUN: llc < %s -march=mips -mcpu=mips32r2 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32-EB
+; RUN: llc < %s -march=mipsel -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32R6-EL
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -relocation-model=pic | FileCheck %s -check-prefixes=ALL,MIPS32R6-EB
%struct.S2 = type { %struct.S1, %struct.S1 }
%struct.S1 = type { i8, i8 }
%struct.S4 = type { [7 x i8] }
diff --git a/llvm/test/MC/Mips/elf_header.s b/llvm/test/MC/Mips/elf_header.s
index eb6252061c4b..a7dfeaa4ca92 100644
--- a/llvm/test/MC/Mips/elf_header.s
+++ b/llvm/test/MC/Mips/elf_header.s
@@ -1,5 +1,5 @@
# Default ABI for MIPS32 is O32.
-# RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS1 %s
+# RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985 %s
# RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips2 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS2 %s
# RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips3 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS3,32BITMODE %s
# RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips4 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS4,32BITMODE %s
@@ -16,7 +16,7 @@
# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r6 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,LE,O32,NAN2008,MIPS32R6 %s
# Selected ABI O32 takes precedence over target triple.
-# FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips1 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS1 %s
+# FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips1 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985 %s
# FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips2 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS2 %s
# FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips3 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS3,32BITMODE %s
# FIXME: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips4 -target-abi=o32 %s -o - | llvm-readobj -h - | FileCheck --check-prefixes=ALL,ELF32,BE,O32,NAN1985,MIPS4,32BITMODE %s
@@ -139,5 +139,6 @@
# OCTEON-NEXT: EF_MIPS_MACH_OCTEON
+# NAN1985-NOT: EF_MIPS_NAN2008
# NAN2008-NEXT: EF_MIPS_NAN2008
# ALL-NEXT: ]
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