[llvm] d7d6ac5 - [AMDGPU] Define and use names for export targets. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 12 11:57:28 PST 2020
Author: Jay Foad
Date: 2020-11-12T19:57:14Z
New Revision: d7d6ac562477f71879bc72ea11bc0861b41382a0
URL: https://github.com/llvm/llvm-project/commit/d7d6ac562477f71879bc72ea11bc0861b41382a0
DIFF: https://github.com/llvm/llvm-project/commit/d7d6ac562477f71879bc72ea11bc0861b41382a0.diff
LOG: [AMDGPU] Define and use names for export targets. NFC.
Differential Revision: https://reviews.llvm.org/D91289
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUExportClustering.cpp
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/SIDefines.h
llvm/lib/Target/AMDGPU/SIInsertSkips.cpp
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUExportClustering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUExportClustering.cpp
index e0f157608a33..685308b5d128 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUExportClustering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUExportClustering.cpp
@@ -33,7 +33,7 @@ static bool isExport(const SUnit &SU) {
static bool isPositionExport(const SIInstrInfo *TII, SUnit *SU) {
const MachineInstr *MI = SU->getInstr();
int Imm = TII->getNamedOperand(*MI, AMDGPU::OpName::tgt)->getImm();
- return Imm >= 12 && Imm <= 15;
+ return Imm >= AMDGPU::Exp::ET_POS0 && Imm <= AMDGPU::Exp::ET_POS3;
}
static void sortChain(const SIInstrInfo *TII, SmallVector<SUnit *, 8> &Chain,
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 71392dd7a75f..caa56cf19a42 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -5840,21 +5840,21 @@ OperandMatchResultTy AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
uint8_t &Val) {
if (Str == "null") {
- Val = 9;
+ Val = Exp::ET_NULL;
return MatchOperand_Success;
}
if (Str.startswith("mrt")) {
Str = Str.drop_front(3);
if (Str == "z") { // == mrtz
- Val = 8;
+ Val = Exp::ET_MRTZ;
return MatchOperand_Success;
}
if (Str.getAsInteger(10, Val))
return MatchOperand_ParseFail;
- if (Val > 7)
+ if (Val > Exp::ET_MRT7)
return MatchOperand_ParseFail;
return MatchOperand_Success;
@@ -5865,15 +5865,15 @@ OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
if (Str.getAsInteger(10, Val))
return MatchOperand_ParseFail;
- if (Val > 4 || (Val == 4 && !isGFX10()))
+ if (Val > (isGFX10() ? 4 : 3))
return MatchOperand_ParseFail;
- Val += 12;
+ Val += Exp::ET_POS0;
return MatchOperand_Success;
}
if (isGFX10() && Str == "prim") {
- Val = 20;
+ Val = Exp::ET_PRIM;
return MatchOperand_Success;
}
@@ -5885,7 +5885,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
if (Val >= 32)
return MatchOperand_ParseFail;
- Val += 32;
+ Val += Exp::ET_PARAM0;
return MatchOperand_Success;
}
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index ded6b17ae545..5e87f2dd96cf 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -1016,18 +1016,19 @@ void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
// This is really a 6 bit field.
uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1);
- if (Tgt <= 7)
- O << " mrt" << Tgt;
- else if (Tgt == 8)
+ if (Tgt <= Exp::ET_MRT7)
+ O << " mrt" << Tgt - Exp::ET_MRT0;
+ else if (Tgt == Exp::ET_MRTZ)
O << " mrtz";
- else if (Tgt == 9)
+ else if (Tgt == Exp::ET_NULL)
O << " null";
- else if ((Tgt >= 12 && Tgt <= 15) || (Tgt == 16 && AMDGPU::isGFX10(STI)))
- O << " pos" << Tgt - 12;
- else if (AMDGPU::isGFX10(STI) && Tgt == 20)
+ else if (Tgt >= Exp::ET_POS0 &&
+ Tgt <= (isGFX10(STI) ? Exp::ET_POS4 : Exp::ET_POS3))
+ O << " pos" << Tgt - Exp::ET_POS0;
+ else if (isGFX10(STI) && Tgt == Exp::ET_PRIM)
O << " prim";
- else if (Tgt >= 32 && Tgt <= 63)
- O << " param" << Tgt - 32;
+ else if (Tgt >= Exp::ET_PARAM0 && Tgt <= Exp::ET_PARAM31)
+ O << " param" << Tgt - Exp::ET_PARAM0;
else {
// Reserved values 10, 11
O << " invalid_target_" << Tgt;
diff --git a/llvm/lib/Target/AMDGPU/SIDefines.h b/llvm/lib/Target/AMDGPU/SIDefines.h
index 44cb2398dbcf..b5087d32964d 100644
--- a/llvm/lib/Target/AMDGPU/SIDefines.h
+++ b/llvm/lib/Target/AMDGPU/SIDefines.h
@@ -688,6 +688,23 @@ enum DppFiMode {
};
} // namespace DPP
+
+namespace Exp {
+
+enum Target {
+ ET_MRT0 = 0,
+ ET_MRT7 = 7,
+ ET_MRTZ = 8,
+ ET_NULL = 9,
+ ET_POS0 = 12,
+ ET_POS3 = 15,
+ ET_POS4 = 16, // GFX10+
+ ET_PRIM = 20, // GFX10+
+ ET_PARAM0 = 32,
+ ET_PARAM31 = 63,
+};
+
+} // namespace Exp
} // namespace AMDGPU
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028
diff --git a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp
index 5bb5165bae52..07e884787220 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertSkips.cpp
@@ -170,7 +170,7 @@ static void generatePsEndPgm(MachineBasicBlock &MBB,
const SIInstrInfo *TII) {
// Generate "null export; s_endpgm".
BuildMI(MBB, I, DL, TII->get(AMDGPU::EXP_DONE))
- .addImm(0x09) // V_008DFC_SQ_EXP_NULL
+ .addImm(AMDGPU::Exp::ET_NULL)
.addReg(AMDGPU::VGPR0, RegState::Undef)
.addReg(AMDGPU::VGPR0, RegState::Undef)
.addReg(AMDGPU::VGPR0, RegState::Undef)
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 41bd6af94e09..5b4ca5bda247 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -1325,9 +1325,9 @@ void SIInsertWaitcnts::updateEventWaitcntAfter(MachineInstr &Inst,
}
} else if (SIInstrInfo::isEXP(Inst)) {
int Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::tgt)->getImm();
- if (Imm >= 32 && Imm <= 63)
+ if (Imm >= AMDGPU::Exp::ET_PARAM0 && Imm <= AMDGPU::Exp::ET_PARAM31)
ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_PARAM_ACCESS, Inst);
- else if (Imm >= 12 && Imm <= 15)
+ else if (Imm >= AMDGPU::Exp::ET_POS0 && Imm <= AMDGPU::Exp::ET_POS3)
ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_POS_ACCESS, Inst);
else
ScoreBrackets->updateByEvent(TII, TRI, MRI, EXP_GPR_LOCK, Inst);
More information about the llvm-commits
mailing list