[PATCH] D91301: [VE] Change the default type of v64 register class

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka.
kaz7 added projects: LLVM, VE.
Herald added subscribers: llvm-commits, hiraditya.
kaz7 requested review of this revision.

Change the default type of v64 register class from v512i32 to v256f64.
Add a regression test also.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D91301

Files:
  llvm/lib/Target/VE/VERegisterInfo.td
  llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst-reg.ll


Index: llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst-reg.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/VE/Scalar/inlineasm-vldvst-reg.ll
@@ -0,0 +1,18 @@
+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=ve -mattr=+vpu -o /dev/null -debug-only=selectiondag 2>&1 | FileCheck %s
+
+;; Check that a vector register is not bitcasted or assigned to v512* type
+;; like below.  Because, inline asm assigns registers by not a type but
+;; register class.
+;;
+;;   t26: ch,glue = inlineasm t25, TargetExternalSymbol:i64'vld $0, $2, $1', MDNode:ch<null>, TargetConstant:i64<1>, TargetConstant:i32<589834>, Register:v512i32 %4, TargetConstant:i32<262153>, Register:i64 %5, TargetConstant:i32<262153>, Register:i64 %6, t25:1
+;;   t28: v512i32 = bitcast t27
+
+define void @vldvst(i8* %p, i64 %i) nounwind {
+; CHECK-NOT: v512
+  %lvl = tail call i64 asm sideeffect "lea $0, 256", "=r"() nounwind
+  tail call void asm sideeffect "lvl $0", "r"(i64 %lvl) nounwind
+  %1 = tail call <256 x double> asm sideeffect "vld $0, $2, $1", "=v,r,r"(i8* %p, i64 %i) nounwind
+  tail call void asm sideeffect "vst $0, $2, $1", "v,r,r"(<256 x double> %1, i8* %p, i64 %i) nounwind
+  ret void
+}
Index: llvm/lib/Target/VE/VERegisterInfo.td
===================================================================
--- llvm/lib/Target/VE/VERegisterInfo.td
+++ llvm/lib/Target/VE/VERegisterInfo.td
@@ -183,8 +183,9 @@
                              (sequence "Q%u", 4, 16))>;
 
 def V64 : RegisterClass<"VE",
-                        [v512i32, v512f32,
-                         v256i64, v256i32, v256f32, v256f64,
+                        [v256f64, // default type for vector registers
+                         v512i32, v512f32,
+                         v256i64, v256i32, v256f32, /* v256f64, */
                          v128i64, v128i32, v128f32, v128f64,
                          v64i64,  v64i32,  v64f32,  v64f64,
                          v32i64,  v32i32,  v32f32,  v32f64,


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