[PATCH] D90738: [RISCV] Support Zfh half-precision floating-point extension.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:655
 
-    if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD() ||
-        MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) {
+    if (MF.getSubtarget<RISCVSubtarget>().hasStdExtZfh() ||
+        MF.getSubtarget<RISCVSubtarget>().hasStdExtF() ||
----------------
Is it sufficient to just check hasStdExtF here?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2844
   // use the ABI names in register constraint lists.
   if (Subtarget.hasStdExtF() || Subtarget.hasStdExtD()) {
     unsigned FReg = StringSwitch<unsigned>(Constraint.lower())
----------------
Checking D here is also unnecessary isn't it?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90738/new/

https://reviews.llvm.org/D90738