[llvm] 3e5b8d8 - [AArch4] Regenerate test checks for f16-imm.ll. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 11 11:42:25 PST 2020
Author: David Green
Date: 2020-11-11T19:42:12Z
New Revision: 3e5b8d83f752bd989b77300646b412dc4f6a8175
URL: https://github.com/llvm/llvm-project/commit/3e5b8d83f752bd989b77300646b412dc4f6a8175
DIFF: https://github.com/llvm/llvm-project/commit/3e5b8d83f752bd989b77300646b412dc4f6a8175.diff
LOG: [AArch4] Regenerate test checks for f16-imm.ll. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/f16-imm.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/f16-imm.ll b/llvm/test/CodeGen/AArch64/f16-imm.ll
index edc070a1ea76..9b9de27176a9 100644
--- a/llvm/test/CodeGen/AArch64/f16-imm.ll
+++ b/llvm/test/CodeGen/AArch64/f16-imm.ll
@@ -1,105 +1,115 @@
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ILLEGAL
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+zcz | FileCheck %s --check-prefix=CHECK-ZCZ
-; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefix=CHECK-NOFP16 --check-prefix=CHECK-ILLEGAL
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-NOZCZ
+; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=+fullfp16,+zcz | FileCheck %s --check-prefixes=CHECK,CHECK-FP16,CHECK-ZCZ
+; RUN: llc < %s -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFP16
define half @Const0() {
+; CHECK-NOZCZ-LABEL: Const0:
+; CHECK-NOZCZ: // %bb.0: // %entry
+; CHECK-NOZCZ-NEXT: fmov h0, wzr
+; CHECK-NOZCZ-NEXT: ret
+;
+; CHECK-ZCZ-LABEL: Const0:
+; CHECK-ZCZ: // %bb.0: // %entry
+; CHECK-ZCZ-NEXT: movi v0.2d, #0000000000000000
+; CHECK-ZCZ-NEXT: ret
+;
+; CHECK-NOFP16-LABEL: Const0:
+; CHECK-NOFP16: // %bb.0: // %entry
+; CHECK-NOFP16-NEXT: adrp x8, .LCPI0_0
+; CHECK-NOFP16-NEXT: ldr h0, [x8, :lo12:.LCPI0_0]
+; CHECK-NOFP16-NEXT: ret
entry:
ret half 0xH0000
}
-; CHECK-DAG-ILLEGAL-LABEL: Const0:
-; CHECK-DAG-ILLEGAL-NEXT: fmov h0, wzr
-; CHECK-DAG-ILLEGAL-NEXT: ret
-
-; CHECK-ZCZ-LABEL: Const0:
-; CHECK-ZCZ: movi v0.2d, #0000000000000000
-; CHECK-ZCZ-NEXT: ret
define half @Const1() {
+; CHECK-FP16-LABEL: Const1:
+; CHECK-FP16: // %bb.0: // %entry
+; CHECK-FP16-NEXT: fmov h0, #1.00000000
+; CHECK-FP16-NEXT: ret
+;
+; CHECK-NOFP16-LABEL: Const1:
+; CHECK-NOFP16: // %bb.0: // %entry
+; CHECK-NOFP16-NEXT: adrp x8, .LCPI1_0
+; CHECK-NOFP16-NEXT: ldr h0, [x8, :lo12:.LCPI1_0]
+; CHECK-NOFP16-NEXT: ret
entry:
ret half 0xH3C00
}
-; CHECK-DAG-LABEL: Const1:
-; CHECK-DAG-NEXT: fmov h0, #1.00000000
-; CHECK-DAG-NEXT: ret
-
-; CHECK-NOFP16: .[[LBL1:LCPI1_[0-9]]]:
-; CHECK-NOFP16-NEXT: .hword 0x3c00 // half 1
-; CHECK-NOFP16-LABEL: Const1:
-; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL1]]
-; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL1]]]
define half @Const2() {
+; CHECK-FP16-LABEL: Const2:
+; CHECK-FP16: // %bb.0: // %entry
+; CHECK-FP16-NEXT: fmov h0, #0.12500000
+; CHECK-FP16-NEXT: ret
+;
+; CHECK-NOFP16-LABEL: Const2:
+; CHECK-NOFP16: // %bb.0: // %entry
+; CHECK-NOFP16-NEXT: adrp x8, .LCPI2_0
+; CHECK-NOFP16-NEXT: ldr h0, [x8, :lo12:.LCPI2_0]
+; CHECK-NOFP16-NEXT: ret
entry:
ret half 0xH3000
}
-; CHECK-DAG-LABEL: Const2:
-; CHECK-DAG-NEXT: fmov h0, #0.12500000
-; CHECK-DAG-NEXT: ret
-
-; CHECK-NOFP16: .[[LBL2:LCPI2_[0-9]]]:
-; CHECK-NOFP16-NEXT: .hword 0x3000 // half 0.125
-; CHECK-NOFP16-LABEL: Const2:
-; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL2]]
-; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL2]]]
define half @Const3() {
+; CHECK-FP16-LABEL: Const3:
+; CHECK-FP16: // %bb.0: // %entry
+; CHECK-FP16-NEXT: fmov h0, #30.00000000
+; CHECK-FP16-NEXT: ret
+;
+; CHECK-NOFP16-LABEL: Const3:
+; CHECK-NOFP16: // %bb.0: // %entry
+; CHECK-NOFP16-NEXT: adrp x8, .LCPI3_0
+; CHECK-NOFP16-NEXT: ldr h0, [x8, :lo12:.LCPI3_0]
+; CHECK-NOFP16-NEXT: ret
entry:
ret half 0xH4F80
}
-; CHECK-DAG-LABEL: Const3:
-; CHECK-DAG-NEXT: fmov h0, #30.00000000
-; CHECK-DAG-NEXT: ret
-
-; CHECK-NOFP16: .[[LBL3:LCPI3_[0-9]]]:
-; CHECK-NOFP16-NEXT: .hword 0x4f80 // half 30
-; CHECK-NOFP16-LABEL: Const3:
-; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL3]]
-; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL3]]]
-
define half @Const4() {
+; CHECK-FP16-LABEL: Const4:
+; CHECK-FP16: // %bb.0: // %entry
+; CHECK-FP16-NEXT: fmov h0, #31.00000000
+; CHECK-FP16-NEXT: ret
+;
+; CHECK-NOFP16-LABEL: Const4:
+; CHECK-NOFP16: // %bb.0: // %entry
+; CHECK-NOFP16-NEXT: adrp x8, .LCPI4_0
+; CHECK-NOFP16-NEXT: ldr h0, [x8, :lo12:.LCPI4_0]
+; CHECK-NOFP16-NEXT: ret
entry:
ret half 0xH4FC0
}
-; CHECK-DAG-LABEL: Const4:
-; CHECK-DAG-NEXT: fmov h0, #31.00000000
-; CHECK-DAG-NEXT: ret
-
-; CHECK-NOFP16: .[[LBL4:LCPI4_[0-9]]]:
-; CHECK-NOFP16-NEXT: .hword 0x4fc0 // half 31
-; CHECK-NOFP16-LABEL: Const4:
-; CHECK-NOFP16: adrp x[[NUM:[0-9]+]], .[[LBL4]]
-; CHECK-NOFP16-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL4]]]
define half @Const5() {
+; CHECK-LABEL: Const5:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adrp x8, .LCPI5_0
+; CHECK-NEXT: ldr h0, [x8, :lo12:.LCPI5_0]
+; CHECK-NEXT: ret
entry:
ret half 0xH2FF0
}
-; CHECK-ILLEGAL: .[[LBL5:LCPI5_[0-9]]]:
-; CHECK-ILLEGAL-NEXT: .hword 0x2ff0 // half 0.12402
-; CHECK-ILLEGAL-LABEL: Const5:
-; CHECK-ILLEGAL: adrp x[[NUM:[0-9]+]], .[[LBL5]]
-; CHECK-ILLEGAL-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL5]]]
define half @Const6() {
+; CHECK-LABEL: Const6:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adrp x8, .LCPI6_0
+; CHECK-NEXT: ldr h0, [x8, :lo12:.LCPI6_0]
+; CHECK-NEXT: ret
entry:
ret half 0xH4FC1
}
-; CHECK-ILLEGAL: .[[LBL6:LCPI6_[0-9]]]:
-; CHECK-ILLEGAL-NEXT: .hword 0x4fc1 // half 31.016
-; CHECK-ILLEGAL-LABEL: Const6:
-; CHECK-ILLEGAL: adrp x[[NUM:[0-9]+]], .[[LBL6]]
-; CHECK-ILLEGAL-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL6]]]
-
define half @Const7() {
+; CHECK-LABEL: Const7:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: adrp x8, .LCPI7_0
+; CHECK-NEXT: ldr h0, [x8, :lo12:.LCPI7_0]
+; CHECK-NEXT: ret
entry:
ret half 0xH5000
}
-; CHECK-ILLEGAL: .[[LBL7:LCPI7_[0-9]]]:
-; CHECK-ILLEGAL-NEXT: .hword 0x5000 // half 32
-; CHECK-ILLEGAL-LABEL: Const7:
-; CHECK-ILLEGAL: adrp x[[NUM:[0-9]+]], .[[LBL7]]
-; CHECK-ILLEGAL-NEXT: ldr h0, [x[[NUM]], :lo12:.[[LBL7]]]
-
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