[llvm] 2b33ea6 - [AMDGPU] Split exp instructions out into their own tablegen file. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 11 09:14:07 PST 2020
Author: Jay Foad
Date: 2020-11-11T17:13:40Z
New Revision: 2b33ea693586bfc641444296389824669f617151
URL: https://github.com/llvm/llvm-project/commit/2b33ea693586bfc641444296389824669f617151
DIFF: https://github.com/llvm/llvm-project/commit/2b33ea693586bfc641444296389824669f617151.diff
LOG: [AMDGPU] Split exp instructions out into their own tablegen file. NFC.
Differential Revision: https://reviews.llvm.org/D91246
Added:
llvm/lib/Target/AMDGPU/EXPInstructions.td
Modified:
llvm/lib/Target/AMDGPU/SIInstrFormats.td
llvm/lib/Target/AMDGPU/SIInstrInfo.td
llvm/lib/Target/AMDGPU/SIInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td
new file mode 100644
index 000000000000..90e3309a8eba
--- /dev/null
+++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td
@@ -0,0 +1,106 @@
+//===-- EXPInstructions.td - Export Instruction Definitions ---------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// EXP classes
+//===----------------------------------------------------------------------===//
+
+class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
+ InstSI<outs, ins, asm, pattern> {
+ let EXP = 1;
+ let EXP_CNT = 1;
+ let mayLoad = 0; // Set to 1 if done bit is set.
+ let mayStore = 1;
+ let UseNamedOperandTable = 1;
+ let Uses = [EXEC];
+ let SchedRW = [WriteExport];
+}
+
+class EXP_Helper<bit done> : EXPCommon<
+ (outs),
+ (ins exp_tgt:$tgt,
+ ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
+ exp_vm:$vm, exp_compr:$compr, i32imm:$en),
+ "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")#"$compr$vm", []> {
+ let AsmMatchConverter = "cvtExp";
+}
+
+// Split EXP instruction into EXP and EXP_DONE so we can set
+// mayLoad for done=1.
+multiclass EXP_m<bit done> {
+ let mayLoad = done, DisableWQM = 1 in {
+ let isPseudo = 1, isCodeGenOnly = 1 in {
+ def "" : EXP_Helper<done>,
+ SIMCInstr <NAME, SIEncodingFamily.NONE>;
+ }
+
+ let done = done in {
+ def _si : EXP_Helper<done>,
+ SIMCInstr <NAME, SIEncodingFamily.SI>,
+ EXPe {
+ let AssemblerPredicate = isGFX6GFX7;
+ let DecoderNamespace = "GFX6GFX7";
+ }
+
+ def _vi : EXP_Helper<done>,
+ SIMCInstr <NAME, SIEncodingFamily.VI>,
+ EXPe_vi {
+ let AssemblerPredicate = isGFX8GFX9;
+ let DecoderNamespace = "GFX8";
+ }
+
+ def _gfx10 : EXP_Helper<done>,
+ SIMCInstr <NAME, SIEncodingFamily.GFX10>,
+ EXPe {
+ let AssemblerPredicate = isGFX10Plus;
+ let DecoderNamespace = "GFX10";
+ }
+ }
+ }
+}
+
+//===----------------------------------------------------------------------===//
+// EXP Instructions
+//===----------------------------------------------------------------------===//
+
+defm EXP : EXP_m<0>;
+defm EXP_DONE : EXP_m<1>;
+
+//===----------------------------------------------------------------------===//
+// EXP Patterns
+//===----------------------------------------------------------------------===//
+
+class ExpPattern<ValueType vt, Instruction Inst, int done_val> : GCNPat<
+ (int_amdgcn_exp timm:$tgt, timm:$en,
+ (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
+ (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
+ done_val, timm:$vm),
+ (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
+ ExpSrc2:$src2, ExpSrc3:$src3, timm:$vm, 0, timm:$en)
+>;
+
+class ExpComprPattern<ValueType vt, Instruction Inst, int done_val> : GCNPat<
+ (int_amdgcn_exp_compr timm:$tgt, timm:$en,
+ (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
+ done_val, timm:$vm),
+ (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
+ (IMPLICIT_DEF), (IMPLICIT_DEF), timm:$vm, 1, timm:$en)
+>;
+
+// FIXME: The generated DAG matcher seems to have strange behavior
+// with a 1-bit literal to match, so use a -1 for checking a true
+// 1-bit value.
+def : ExpPattern<i32, EXP, 0>;
+def : ExpPattern<i32, EXP_DONE, -1>;
+def : ExpPattern<f32, EXP, 0>;
+def : ExpPattern<f32, EXP_DONE, -1>;
+
+def : ExpComprPattern<v2i16, EXP, 0>;
+def : ExpComprPattern<v2i16, EXP_DONE, -1>;
+def : ExpComprPattern<v2f16, EXP, 0>;
+def : ExpComprPattern<v2f16, EXP_DONE, -1>;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index 8e0dcbb9dc74..79cd6a5bb844 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -363,15 +363,4 @@ class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> :
let VALU = 1;
}
-class EXPCommon<dag outs, dag ins, string asm, list<dag> pattern> :
- InstSI<outs, ins, asm, pattern> {
- let EXP = 1;
- let EXP_CNT = 1;
- let mayLoad = 0; // Set to 1 if done bit is set.
- let mayStore = 1;
- let UseNamedOperandTable = 1;
- let Uses = [EXEC];
- let SchedRW = [WriteExport];
-}
-
} // End Uses = [EXEC]
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index b183a5c52b48..b2bc21975a53 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -1419,53 +1419,6 @@ class SIMCInstr <string pseudo, int subtarget> {
int Subtarget = subtarget;
}
-//===----------------------------------------------------------------------===//
-// EXP classes
-//===----------------------------------------------------------------------===//
-
-class EXP_Helper<bit done> : EXPCommon<
- (outs),
- (ins exp_tgt:$tgt,
- ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
- exp_vm:$vm, exp_compr:$compr, i32imm:$en),
- "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")#"$compr$vm", []> {
- let AsmMatchConverter = "cvtExp";
-}
-
-// Split EXP instruction into EXP and EXP_DONE so we can set
-// mayLoad for done=1.
-multiclass EXP_m<bit done> {
- let mayLoad = done, DisableWQM = 1 in {
- let isPseudo = 1, isCodeGenOnly = 1 in {
- def "" : EXP_Helper<done>,
- SIMCInstr <NAME, SIEncodingFamily.NONE>;
- }
-
- let done = done in {
- def _si : EXP_Helper<done>,
- SIMCInstr <NAME, SIEncodingFamily.SI>,
- EXPe {
- let AssemblerPredicate = isGFX6GFX7;
- let DecoderNamespace = "GFX6GFX7";
- }
-
- def _vi : EXP_Helper<done>,
- SIMCInstr <NAME, SIEncodingFamily.VI>,
- EXPe_vi {
- let AssemblerPredicate = isGFX8GFX9;
- let DecoderNamespace = "GFX8";
- }
-
- def _gfx10 : EXP_Helper<done>,
- SIMCInstr <NAME, SIEncodingFamily.GFX10>,
- EXPe {
- let AssemblerPredicate = isGFX10Plus;
- let DecoderNamespace = "GFX10";
- }
- }
- }
-}
-
//===----------------------------------------------------------------------===//
// Vector ALU classes
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 1fdb5ed37be4..5825d21e3339 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -19,43 +19,7 @@ include "VOPInstructions.td"
include "SMInstructions.td"
include "FLATInstructions.td"
include "BUFInstructions.td"
-
-//===----------------------------------------------------------------------===//
-// EXP Instructions
-//===----------------------------------------------------------------------===//
-
-defm EXP : EXP_m<0>;
-defm EXP_DONE : EXP_m<1>;
-
-class ExpPattern<ValueType vt, Instruction Inst, int done_val> : GCNPat<
- (int_amdgcn_exp timm:$tgt, timm:$en,
- (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
- (vt ExpSrc2:$src2), (vt ExpSrc3:$src3),
- done_val, timm:$vm),
- (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
- ExpSrc2:$src2, ExpSrc3:$src3, timm:$vm, 0, timm:$en)
->;
-
-class ExpComprPattern<ValueType vt, Instruction Inst, int done_val> : GCNPat<
- (int_amdgcn_exp_compr timm:$tgt, timm:$en,
- (vt ExpSrc0:$src0), (vt ExpSrc1:$src1),
- done_val, timm:$vm),
- (Inst timm:$tgt, ExpSrc0:$src0, ExpSrc1:$src1,
- (IMPLICIT_DEF), (IMPLICIT_DEF), timm:$vm, 1, timm:$en)
->;
-
-// FIXME: The generated DAG matcher seems to have strange behavior
-// with a 1-bit literal to match, so use a -1 for checking a true
-// 1-bit value.
-def : ExpPattern<i32, EXP, 0>;
-def : ExpPattern<i32, EXP_DONE, -1>;
-def : ExpPattern<f32, EXP, 0>;
-def : ExpPattern<f32, EXP_DONE, -1>;
-
-def : ExpComprPattern<v2i16, EXP, 0>;
-def : ExpComprPattern<v2i16, EXP_DONE, -1>;
-def : ExpComprPattern<v2f16, EXP, 0>;
-def : ExpComprPattern<v2f16, EXP_DONE, -1>;
+include "EXPInstructions.td"
//===----------------------------------------------------------------------===//
// VINTRP Instructions
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