[PATCH] D91255: [AArch64] Rearrange (dup(sext/zext)) to (sext/zext(dup))

[Nicholas Guy via Phabricator via llvm-commits]

NickGuy added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10584-10586
+
+      // TODO Why can this sometimes fail?
+      if(isa<Instruction>(&Shuffle->getOperandUse(0)))
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In a number of tests, this line is hit more than a few times. Only 1 of which it fails on. Using .dump() to try and identify why didn't help, as it appears to be the same style as the others that pass (e.g. %tmp3 = sext <8 x i8> %arg to <8 x i16>)
If anyone can provide insight to this, I would greatly appreciate it :)


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15020-15029
+static SDValue performDUPCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) {
+  auto Operand = N->getOperand(0);
+  auto Opcode = Operand.getOpcode();
+  bool IsSext = Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_INREG || Opcode == ISD::AssertSext;
+  if(IsSext || Opcode == ISD::ZERO_EXTEND || Opcode == ISD::AssertZext) {
+    return performDUPSextCombine(N, DAG, IsSext);
+  }
----------------
I'm unsure as to when PerformDAGCombine is invoked. If this function generates a new DUP node, would this function then be invoked with that node? Or does this function need a bit more scaffolding to support this case?


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  https://reviews.llvm.org/D91255/new/

https://reviews.llvm.org/D91255