[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir:31
+    %5:vr = IMPLICIT_DEF
+    %4:vr = PseudoVLE64_V_M1 %5, %1, $noreg, %3, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
+    %7:vr = IMPLICIT_DEF
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craig.topper wrote:
> I'm a little concerned that Machine IR immediately out of SelectionDAG doesn't reflect the real semantics. The Pseudos should implicit-def $vl and $type and not implicit use them. As long as their fused with vsetvli, they should have the semantics of the pair.
> 
> But I don't know how to get the right semantics without having 2 sets of pseudos. How many instructions would that come out to?
One option could be to remove their `Uses=[VL, VTYPE]` but then they would come out without those implicit uses which is not ideal either but I wonder if this might lead to other issues elsewhere (e.g. in the machine inst verifier?)

Perhaps we could hook in the InstrEmitter (or whoever creates the actual MachineInstrs) somehow and add the implicit-vdefs. Then in the custom inserter remove those and put the implicit-uses after we have emitted vsetvli.


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  https://reviews.llvm.org/D89449/new/

https://reviews.llvm.org/D89449