[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 10 11:14:33 PST 2020
craig.topper added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir:31
+ %5:vr = IMPLICIT_DEF
+ %4:vr = PseudoVLE64_V_M1 %5, %1, $noreg, %3, 64, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8)
+ %7:vr = IMPLICIT_DEF
----------------
I'm a little concerned that Machine IR immediately out of SelectionDAG doesn't reflect the real semantics. The Pseudos should implicit-def $vl and $type and not implicit use them. As long as their fused with vsetvli, they should have the semantics of the pair.
But I don't know how to get the right semantics without having 2 sets of pseudos. How many instructions would that come out to?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D89449/new/
https://reviews.llvm.org/D89449
More information about the llvm-commits
mailing list